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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
| commit | 7d0344704a9ecc566d82ad43ec44b4becbaf4d77 (patch) | |
| tree | 4281e9fe0ff9480698ed697027e411da73e78d47 /src/cpu/checker | |
| parent | 3436de0c2ad467c65066e48969a7c12bdbbb3d26 (diff) | |
| download | gem5-7d0344704a9ecc566d82ad43ec44b4becbaf4d77.tar.xz | |
arch, cpu: Add support for flattening misc register indexes.
With ARMv8 support the same misc register id results in accessing different
registers depending on the current mode of the processor. This patch adds
the same orthogonality to the misc register file as the others (int, float, cc).
For all the othre ISAs this is currently a null-implementation.
Additionally, a system variable is added to all the ISA objects.
Diffstat (limited to 'src/cpu/checker')
| -rw-r--r-- | src/cpu/checker/thread_context.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index c06e03fc6..5c695c750 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -300,6 +300,7 @@ class CheckerThreadContext : public ThreadContext int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); } int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); } int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); } + int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); } unsigned readStCondFailures() { return actualTC->readStCondFailures(); } |