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| author | Gabe Black <gabeblack@google.com> | 2018-11-21 16:20:57 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-02-01 01:22:19 +0000 |
| commit | a119a963240a35ab66a5baee3f77cfcd99c6bbbb (patch) | |
| tree | c883d37ed479e92c23d881a48b8f2abec469faf7 /src/cpu/checker | |
| parent | fbdf0b689eb31543292f52c71d14152d8ff1156a (diff) | |
| download | gem5-a119a963240a35ab66a5baee3f77cfcd99c6bbbb.tar.xz | |
cpu, arch: Replace the CCReg type with RegVal.
Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.
Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/checker')
| -rw-r--r-- | src/cpu/checker/cpu.hh | 4 | ||||
| -rw-r--r-- | src/cpu/checker/thread_context.hh | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 30d17bdf6..e32c015bf 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -320,7 +320,7 @@ class CheckerCPU : public BaseCPU, public ExecContext return thread->getWritableVecPredReg(reg); } - CCReg + RegVal readCCRegOperand(const StaticInst *si, int idx) override { const RegId& reg = si->srcRegIdx(idx); @@ -379,7 +379,7 @@ class CheckerCPU : public BaseCPU, public ExecContext } void - setCCRegOperand(const StaticInst *si, int idx, CCReg val) override + setCCRegOperand(const StaticInst *si, int idx, RegVal val) override { const RegId& reg = si->destRegIdx(idx); assert(reg.isCCReg()); diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 99506c1c8..0983d03ef 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -269,7 +269,7 @@ class CheckerThreadContext : public ThreadContext VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override { return actualTC->getWritableVecPredReg(reg); } - CCReg readCCReg(int reg_idx) + RegVal readCCReg(int reg_idx) { return actualTC->readCCReg(reg_idx); } void @@ -308,7 +308,7 @@ class CheckerThreadContext : public ThreadContext } void - setCCReg(int reg_idx, CCReg val) + setCCReg(int reg_idx, RegVal val) { actualTC->setCCReg(reg_idx, val); checkerTC->setCCReg(reg_idx, val); @@ -450,10 +450,10 @@ class CheckerThreadContext : public ThreadContext void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override { actualTC->setVecPredRegFlat(idx, val); } - CCReg readCCRegFlat(int idx) + RegVal readCCRegFlat(int idx) { return actualTC->readCCRegFlat(idx); } - void setCCRegFlat(int idx, CCReg val) + void setCCRegFlat(int idx, RegVal val) { actualTC->setCCRegFlat(idx, val); } }; |