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author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:42 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:42 -0400 |
commit | 08c1835bef5caa72dc931ed529e4ed3470989d4f (patch) | |
tree | c7523438790ccf9d6206fe328291bec468d84b48 /src/cpu/checker | |
parent | 670fc52f1812727457eaf6cb4fca1a520a6a8c20 (diff) | |
download | gem5-08c1835bef5caa72dc931ed529e4ed3470989d4f.tar.xz |
cpu: Remove CpuPort and use MasterPort in the CPU classes
This patch changes the port in the CPU classes to use MasterPort
instead of the derived CpuPort. The functions of the CpuPort are now
distributed across the relevant subclasses. The port accessor
functions (getInstPort and getDataPort) now return a MasterPort
instead of a CpuPort. This simplifies creating derivative CPUs that do
not use the CpuPort.
Diffstat (limited to 'src/cpu/checker')
-rw-r--r-- | src/cpu/checker/cpu.cc | 4 | ||||
-rw-r--r-- | src/cpu/checker/cpu.hh | 12 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index f695c24df..c824121be 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -117,13 +117,13 @@ CheckerCPU::setSystem(System *system) } void -CheckerCPU::setIcachePort(CpuPort *icache_port) +CheckerCPU::setIcachePort(MasterPort *icache_port) { icachePort = icache_port; } void -CheckerCPU::setDcachePort(CpuPort *dcache_port) +CheckerCPU::setDcachePort(MasterPort *dcache_port) { dcachePort = dcache_port; } diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 6bd2b7e31..19d3420ec 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -104,11 +104,11 @@ class CheckerCPU : public BaseCPU void setSystem(System *system); - void setIcachePort(CpuPort *icache_port); + void setIcachePort(MasterPort *icache_port); - void setDcachePort(CpuPort *dcache_port); + void setDcachePort(MasterPort *dcache_port); - CpuPort &getDataPort() + MasterPort &getDataPort() { // the checker does not have ports on its own so return the // data port of the actual CPU core @@ -116,7 +116,7 @@ class CheckerCPU : public BaseCPU return *dcachePort; } - CpuPort &getInstPort() + MasterPort &getInstPort() { // the checker does not have ports on its own so return the // data port of the actual CPU core @@ -130,8 +130,8 @@ class CheckerCPU : public BaseCPU System *systemPtr; - CpuPort *icachePort; - CpuPort *dcachePort; + MasterPort *icachePort; + MasterPort *dcachePort; ThreadContext *tc; |