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author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/cpu/checker | |
parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/cpu/checker')
-rw-r--r-- | src/cpu/checker/cpu.hh | 52 | ||||
-rw-r--r-- | src/cpu/checker/cpu_impl.hh | 25 |
2 files changed, 44 insertions, 33 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index e47c88484..3afbc31fb 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -213,26 +213,31 @@ class CheckerCPU : public BaseCPU, public ExecContext IntReg readIntRegOperand(const StaticInst *si, int idx) override { - return thread->readIntReg(si->srcRegIdx(idx)); + RegId reg = si->srcRegIdx(idx); + assert(reg.regClass == IntRegClass); + return thread->readIntReg(reg.regIdx); } FloatReg readFloatRegOperand(const StaticInst *si, int idx) override { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; - return thread->readFloatReg(reg_idx); + RegId reg = si->srcRegIdx(idx); + assert(reg.regClass == FloatRegClass); + return thread->readFloatReg(reg.regIdx); } FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override { - int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; - return thread->readFloatRegBits(reg_idx); + RegId reg = si->srcRegIdx(idx); + assert(reg.regClass == FloatRegClass); + return thread->readFloatRegBits(reg.regIdx); } CCReg readCCRegOperand(const StaticInst *si, int idx) override { - int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; - return thread->readCCReg(reg_idx); + RegId reg = si->srcRegIdx(idx); + assert(reg.regClass == CCRegClass); + return thread->readCCReg(reg.regIdx); } template <class T> @@ -246,30 +251,35 @@ class CheckerCPU : public BaseCPU, public ExecContext void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override { - thread->setIntReg(si->destRegIdx(idx), val); + RegId reg = si->destRegIdx(idx); + assert(reg.regClass == IntRegClass); + thread->setIntReg(reg.regIdx, val); setResult<uint64_t>(val); } void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) override { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; - thread->setFloatReg(reg_idx, val); + RegId reg = si->destRegIdx(idx); + assert(reg.regClass == FloatRegClass); + thread->setFloatReg(reg.regIdx, val); setResult<double>(val); } void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) override { - int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; - thread->setFloatRegBits(reg_idx, val); + RegId reg = si->destRegIdx(idx); + assert(reg.regClass == FloatRegClass); + thread->setFloatRegBits(reg.regIdx, val); setResult<uint64_t>(val); } void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override { - int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; - thread->setCCReg(reg_idx, val); + RegId reg = si->destRegIdx(idx); + assert(reg.regClass == CCRegClass); + thread->setCCReg(reg.regIdx, val); setResult<uint64_t>(val); } @@ -317,25 +327,27 @@ class CheckerCPU : public BaseCPU, public ExecContext MiscReg readMiscRegOperand(const StaticInst *si, int idx) override { - int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; - return thread->readMiscReg(reg_idx); + RegId reg = si->srcRegIdx(idx); + assert(reg.regClass == MiscRegClass); + return thread->readMiscReg(reg.regIdx); } void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val) override { - int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; - return this->setMiscReg(reg_idx, val); + RegId reg = si->destRegIdx(idx); + assert(reg.regClass == MiscRegClass); + return this->setMiscReg(reg.regIdx, val); } #if THE_ISA == MIPS_ISA - MiscReg readRegOtherThread(int misc_reg, ThreadID tid) override + MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid) override { panic("MIPS MT not defined for CheckerCPU.\n"); return 0; } - void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) override + void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid) override { panic("MIPS MT not defined for CheckerCPU.\n"); } diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 5d5900aae..47a088aa6 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -595,41 +595,40 @@ Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val, // We've already popped one dest off the queue, // so do the fix-up then start with the next dest reg; if (start_idx >= 0) { - RegIndex idx = inst->destRegIdx(start_idx); - switch (regIdxToClass(idx)) { + RegId idx = inst->destRegIdx(start_idx); + switch (idx.regClass) { case IntRegClass: - thread->setIntReg(idx, mismatch_val); + thread->setIntReg(idx.regIdx, mismatch_val); break; case FloatRegClass: - thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, mismatch_val); + thread->setFloatRegBits(idx.regIdx, mismatch_val); break; case CCRegClass: - thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val); + thread->setCCReg(idx.regIdx, mismatch_val); break; case MiscRegClass: - thread->setMiscReg(idx - TheISA::Misc_Reg_Base, - mismatch_val); + thread->setMiscReg(idx.regIdx, mismatch_val); break; } } start_idx++; uint64_t res = 0; for (int i = start_idx; i < inst->numDestRegs(); i++) { - RegIndex idx = inst->destRegIdx(i); + RegId idx = inst->destRegIdx(i); inst->template popResult<uint64_t>(res); - switch (regIdxToClass(idx)) { + switch (idx.regClass) { case IntRegClass: - thread->setIntReg(idx, res); + thread->setIntReg(idx.regIdx, res); break; case FloatRegClass: - thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res); + thread->setFloatRegBits(idx.regIdx, res); break; case CCRegClass: - thread->setCCReg(idx - TheISA::CC_Reg_Base, res); + thread->setCCReg(idx.regIdx, res); break; case MiscRegClass: // Try to get the proper misc register index for ARM here... - thread->setMiscReg(idx - TheISA::Misc_Reg_Base, res); + thread->setMiscReg(idx.regIdx, res); break; // else Register is out of range... } |