CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable

Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files.  Also merges with the SE/FS changes.

4 files changed, 48 insertions, 23 deletions

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index b21ceeb92..66341b0e0 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -52,6 +52,7 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "params/CheckerCPU.hh"
+#include "sim/full_system.hh"
 #include "sim/tlb.hh"
 
 using namespace std;
@@ -84,12 +85,7 @@ CheckerCPU::CheckerCPU(Params *p)
     dtb = p->dtb;
     systemPtr = NULL;
     workload = p->workload;
-    // XXX: This is a hack to get this to work some
-    thread = new SimpleThread(this, /* thread_num */ 0,
-            workload.size() ? workload[0] : NULL, itb, dtb);
-
-    tc = thread->getTC();
-    threadContexts.push_back(tc);
+    thread = NULL;
 
     updateOnError = true;
 }
@@ -103,22 +99,29 @@ CheckerCPU::setSystem(System *system)
 {
     systemPtr = system;
 
-    thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
+    if (FullSystem) {
+        thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
+    } else {
+        thread = new SimpleThread(this, 0, systemPtr,
+                                  workload.size() ? workload[0] : NULL,
+                                  itb, dtb);
+    }
 
     tc = thread->getTC();
     threadContexts.push_back(tc);
-    delete thread->kernelStats;
     thread->kernelStats = NULL;
+    // Thread should never be null after this
+    assert(thread != NULL);
 }
 
 void
-CheckerCPU::setIcachePort(Port *icache_port)
+CheckerCPU::setIcachePort(CpuPort *icache_port)
 {
     icachePort = icache_port;
 }
 
 void
-CheckerCPU::setDcachePort(Port *dcache_port)
+CheckerCPU::setDcachePort(CpuPort *dcache_port)
 {
     dcachePort = dcache_port;
 }
@@ -151,7 +154,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
     // Need to account for multiple accesses like the Atomic and TimingSimple
     while (1) {
         memReq = new Request();
-        memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
+        memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
 
         // translate to physical address
         fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 54e446932..c3d3a379e 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -112,13 +112,25 @@ class CheckerCPU : public BaseCPU
 
     System *systemPtr;
 
-    void setIcachePort(Port *icache_port);
+    void setIcachePort(CpuPort *icache_port);
 
-    Port *icachePort;
+    CpuPort *icachePort;
 
-    void setDcachePort(Port *dcache_port);
+    void setDcachePort(CpuPort *dcache_port);
 
-    Port *dcachePort;
+    CpuPort *dcachePort;
+
+    CpuPort &getDataPort()
+    {
+        panic("Not supported on checker!");
+        return *dcachePort;
+    }
+
+    CpuPort &getInstPort()
+    {
+        panic("Not supported on checker!");
+        return *icachePort;
+    }
 
     virtual Port *getPort(const std::string &name, int idx)
     {
@@ -168,7 +180,12 @@ class CheckerCPU : public BaseCPU
     TheISA::TLB* getITBPtr() { return itb; }
     TheISA::TLB* getDTBPtr() { return dtb; }
 
-    virtual Counter totalInstructions() const
+    virtual Counter totalInsts() const
+    {
+        return 0;
+    }
+
+    virtual Counter totalOps() const
     {
         return 0;
     }
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 5688ee674..4f3fa34d2 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -244,6 +244,7 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
                 memReq = new Request(unverifiedInst->threadNumber, fetch_PC,
                                      sizeof(MachInst),
                                      0,
+                                     masterId,
                                      fetch_PC, thread->contextId(),
                                      unverifiedInst->threadNumber);
                 memReq->setVirt(0, fetch_PC, sizeof(MachInst),
@@ -399,11 +400,13 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
 
         // Take any faults here
         if (fault != NoFault) {
-            fault->invoke(tc, curStaticInst);
-            willChangePC = true;
-            newPCState = thread->pcState();
-            DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
-            curMacroStaticInst = StaticInst::nullStaticInstPtr;
+            if (FullSystem) {
+                fault->invoke(tc, curStaticInst);
+                willChangePC = true;
+                newPCState = thread->pcState();
+                DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
+                curMacroStaticInst = StaticInst::nullStaticInstPtr;
+            }
         } else {
            advancePC(fault);
         }
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 0d6fa6e2e..4aed0501c 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -112,7 +112,10 @@ class CheckerThreadContext : public ThreadContext
 
     TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
-    BaseCPU *getCheckerCpuPtr() { return checkerTC->getCpuPtr(); }
+    CheckerCPU *getCheckerCpuPtr()
+    {
+        return checkerCPU;
+    }
 
     Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
 
@@ -130,7 +133,6 @@ class CheckerThreadContext : public ThreadContext
     FSTranslatingPortProxy &getVirtProxy()
     { return actualTC->getVirtProxy(); }
 
-    //XXX: How does this work now?
     void initMemProxies(ThreadContext *tc)
     { actualTC->initMemProxies(tc); }