summaryrefslogtreecommitdiff
path: root/src/cpu/checker
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-06-06 17:32:21 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-06 17:32:21 -0400
commiteb0e416998ce2546c768d2b9d9d8bf3a387a87be (patch)
tree14064a3b184dbc36e9c0576c120ab209734fe45d /src/cpu/checker
parent0f014e4340bb0991716cb0f0feafd48b53e865d7 (diff)
downloadgem5-eb0e416998ce2546c768d2b9d9d8bf3a387a87be.tar.xz
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar. src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext. --HG-- rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
Diffstat (limited to 'src/cpu/checker')
-rw-r--r--src/cpu/checker/cpu.cc28
-rw-r--r--src/cpu/checker/cpu.hh12
-rw-r--r--src/cpu/checker/exec_context.hh184
3 files changed, 111 insertions, 113 deletions
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index c94570d7d..7ae7047e8 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -34,7 +34,7 @@
#include "cpu/base_dyn_inst.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
#include "sim/byteswap.hh"
#include "sim/sim_object.hh"
@@ -62,7 +62,7 @@ CheckerCPU::init()
}
CheckerCPU::CheckerCPU(Params *p)
- : BaseCPU(p), cpuXC(NULL), xcProxy(NULL)
+ : BaseCPU(p), cpuXC(NULL), tc(NULL)
{
memReq = NULL;
@@ -97,17 +97,16 @@ CheckerCPU::setMemory(MemObject *mem)
cpuXC = new CPUExecContext(this, /* thread_num */ 0, process,
/* asid */ 0, mem);
- cpuXC->setStatus(ExecContext::Suspended);
- xcProxy = cpuXC->getProxy();
- execContexts.push_back(xcProxy);
+ cpuXC->setStatus(ThreadContext::Suspended);
+ tc = cpuXC->getTC();
+ threadContexts.push_back(tc);
#else
if (systemPtr) {
cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
- cpuXC->setStatus(ExecContext::Suspended);
- xcProxy = cpuXC->getProxy();
- execContexts.push_back(xcProxy);
- memReq->xc = xcProxy;
+ cpuXC->setStatus(ThreadContext::Suspended);
+ tc = cpuXC->getTC();
+ threadContexts.push_back(tc);
delete cpuXC->kernelStats;
cpuXC->kernelStats = NULL;
}
@@ -123,10 +122,9 @@ CheckerCPU::setSystem(System *system)
if (memPtr) {
cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
- cpuXC->setStatus(ExecContext::Suspended);
- xcProxy = cpuXC->getProxy();
- execContexts.push_back(xcProxy);
- memReq->xc = xcProxy;
+ cpuXC->setStatus(ThreadContext::Suspended);
+ tc = cpuXC->getTC();
+ threadContexts.push_back(tc);
delete cpuXC->kernelStats;
cpuXC->kernelStats = NULL;
}
@@ -742,12 +740,12 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
int misc_reg_idx = miscRegIdxs.front();
miscRegIdxs.pop();
- if (inst->xcBase()->readMiscReg(misc_reg_idx) !=
+ if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
cpuXC->readMiscReg(misc_reg_idx)) {
warn("%lli: Misc reg idx %i (side effect) does not match! "
"Inst: %#x, checker: %#x",
curTick, misc_reg_idx,
- inst->xcBase()->readMiscReg(misc_reg_idx),
+ inst->tcBase()->readMiscReg(misc_reg_idx),
cpuXC->readMiscReg(misc_reg_idx));
handleError();
}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 704580d80..484f4cf04 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -60,7 +60,7 @@ class Process;
#endif // FULL_SYSTEM
template <class>
class BaseDynInst;
-class ExecContext;
+class ThreadContext;
class MemInterface;
class Checkpoint;
class Request;
@@ -76,11 +76,11 @@ class Sampler;
* the values of uncached accesses. In these cases, and with
* instructions marked as "IsUnverifiable", the checker assumes that
* the value from the main CPU's execution is correct and simply
- * copies that value. It provides a CheckerExecContext (see
+ * copies that value. It provides a CheckerThreadContext (see
* checker/exec_context.hh) that provides hooks for updating the
- * Checker's state through any ExecContext accesses. This allows the
+ * Checker's state through any ThreadContext accesses. This allows the
* checker to be able to correctly verify instructions, even with
- * external accesses to the ExecContext that change state.
+ * external accesses to the ThreadContext that change state.
*/
class CheckerCPU : public BaseCPU
{
@@ -132,7 +132,7 @@ class CheckerCPU : public BaseCPU
// execution context
CPUExecContext *cpuXC;
- ExecContext *xcProxy;
+ ThreadContext *tc;
AlphaITB *itb;
AlphaDTB *dtb;
@@ -340,7 +340,7 @@ class CheckerCPU : public BaseCPU
}
bool checkFlags(Request *req);
- ExecContext *xcBase() { return xcProxy; }
+ ThreadContext *tcBase() { return tc; }
CPUExecContext *cpuXCBase() { return cpuXC; }
Result unverifiedResult;
diff --git a/src/cpu/checker/exec_context.hh b/src/cpu/checker/exec_context.hh
index 054739a6a..48890584d 100644
--- a/src/cpu/checker/exec_context.hh
+++ b/src/cpu/checker/exec_context.hh
@@ -31,7 +31,7 @@
#include "cpu/checker/cpu.hh"
#include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
class EndQuiesceEvent;
namespace Kernel {
@@ -39,251 +39,251 @@ namespace Kernel {
};
/**
- * Derived ExecContext class for use with the Checker. The template
- * parameter is the ExecContext class used by the specific CPU being
- * verified. This CheckerExecContext is then used by the main CPU in
- * place of its usual ExecContext class. It handles updating the
- * checker's state any time state is updated through the ExecContext.
+ * Derived ThreadContext class for use with the Checker. The template
+ * parameter is the ThreadContext class used by the specific CPU being
+ * verified. This CheckerThreadContext is then used by the main CPU in
+ * place of its usual ThreadContext class. It handles updating the
+ * checker's state any time state is updated through the ThreadContext.
*/
-template <class XC>
-class CheckerExecContext : public ExecContext
+template <class TC>
+class CheckerThreadContext : public ThreadContext
{
public:
- CheckerExecContext(XC *actual_xc,
+ CheckerThreadContext(TC *actual_tc,
CheckerCPU *checker_cpu)
- : actualXC(actual_xc), checkerXC(checker_cpu->cpuXC),
+ : actualTC(actual_tc), checkerTC(checker_cpu->cpuXC),
checkerCPU(checker_cpu)
{ }
private:
- XC *actualXC;
- CPUExecContext *checkerXC;
+ TC *actualTC;
+ CPUExecContext *checkerTC;
CheckerCPU *checkerCPU;
public:
- BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
+ BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
void setCpuId(int id)
{
- actualXC->setCpuId(id);
- checkerXC->setCpuId(id);
+ actualTC->setCpuId(id);
+ checkerTC->setCpuId(id);
}
- int readCpuId() { return actualXC->readCpuId(); }
+ int readCpuId() { return actualTC->readCpuId(); }
- TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
+ TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
#if FULL_SYSTEM
- System *getSystemPtr() { return actualXC->getSystemPtr(); }
+ System *getSystemPtr() { return actualTC->getSystemPtr(); }
- PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); }
+ PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
- AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
+ AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
- AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
+ AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
- Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); }
+ Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
#else
- Process *getProcessPtr() { return actualXC->getProcessPtr(); }
+ Process *getProcessPtr() { return actualTC->getProcessPtr(); }
#endif
- Status status() const { return actualXC->status(); }
+ Status status() const { return actualTC->status(); }
void setStatus(Status new_status)
{
- actualXC->setStatus(new_status);
- checkerXC->setStatus(new_status);
+ actualTC->setStatus(new_status);
+ checkerTC->setStatus(new_status);
}
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
- void activate(int delay = 1) { actualXC->activate(delay); }
+ void activate(int delay = 1) { actualTC->activate(delay); }
/// Set the status to Suspended.
- void suspend() { actualXC->suspend(); }
+ void suspend() { actualTC->suspend(); }
/// Set the status to Unallocated.
- void deallocate() { actualXC->deallocate(); }
+ void deallocate() { actualTC->deallocate(); }
/// Set the status to Halted.
- void halt() { actualXC->halt(); }
+ void halt() { actualTC->halt(); }
#if FULL_SYSTEM
- void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
+ void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
#endif
- void takeOverFrom(ExecContext *oldContext)
+ void takeOverFrom(ThreadContext *oldContext)
{
- actualXC->takeOverFrom(oldContext);
- checkerXC->takeOverFrom(oldContext);
+ actualTC->takeOverFrom(oldContext);
+ checkerTC->takeOverFrom(oldContext);
}
- void regStats(const std::string &name) { actualXC->regStats(name); }
+ void regStats(const std::string &name) { actualTC->regStats(name); }
- void serialize(std::ostream &os) { actualXC->serialize(os); }
+ void serialize(std::ostream &os) { actualTC->serialize(os); }
void unserialize(Checkpoint *cp, const std::string &section)
- { actualXC->unserialize(cp, section); }
+ { actualTC->unserialize(cp, section); }
#if FULL_SYSTEM
- EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
+ EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
- Tick readLastActivate() { return actualXC->readLastActivate(); }
- Tick readLastSuspend() { return actualXC->readLastSuspend(); }
+ Tick readLastActivate() { return actualTC->readLastActivate(); }
+ Tick readLastSuspend() { return actualTC->readLastSuspend(); }
- void profileClear() { return actualXC->profileClear(); }
- void profileSample() { return actualXC->profileSample(); }
+ void profileClear() { return actualTC->profileClear(); }
+ void profileSample() { return actualTC->profileSample(); }
#endif
- int getThreadNum() { return actualXC->getThreadNum(); }
+ int getThreadNum() { return actualTC->getThreadNum(); }
// @todo: Do I need this?
- MachInst getInst() { return actualXC->getInst(); }
+ MachInst getInst() { return actualTC->getInst(); }
// @todo: Do I need this?
- void copyArchRegs(ExecContext *xc)
+ void copyArchRegs(ThreadContext *tc)
{
- actualXC->copyArchRegs(xc);
- checkerXC->copyArchRegs(xc);
+ actualTC->copyArchRegs(tc);
+ checkerTC->copyArchRegs(tc);
}
void clearArchRegs()
{
- actualXC->clearArchRegs();
- checkerXC->clearArchRegs();
+ actualTC->clearArchRegs();
+ checkerTC->clearArchRegs();
}
//
// New accessors for new decoder.
//
uint64_t readIntReg(int reg_idx)
- { return actualXC->readIntReg(reg_idx); }
+ { return actualTC->readIntReg(reg_idx); }
FloatReg readFloatReg(int reg_idx, int width)
- { return actualXC->readFloatReg(reg_idx, width); }
+ { return actualTC->readFloatReg(reg_idx, width); }
FloatReg readFloatReg(int reg_idx)
- { return actualXC->readFloatReg(reg_idx); }
+ { return actualTC->readFloatReg(reg_idx); }
FloatRegBits readFloatRegBits(int reg_idx, int width)
- { return actualXC->readFloatRegBits(reg_idx, width); }
+ { return actualTC->readFloatRegBits(reg_idx, width); }
FloatRegBits readFloatRegBits(int reg_idx)
- { return actualXC->readFloatRegBits(reg_idx); }
+ { return actualTC->readFloatRegBits(reg_idx); }
void setIntReg(int reg_idx, uint64_t val)
{
- actualXC->setIntReg(reg_idx, val);
- checkerXC->setIntReg(reg_idx, val);
+ actualTC->setIntReg(reg_idx, val);
+ checkerTC->setIntReg(reg_idx, val);
}
void setFloatReg(int reg_idx, FloatReg val, int width)
{
- actualXC->setFloatReg(reg_idx, val, width);
- checkerXC->setFloatReg(reg_idx, val, width);
+ actualTC->setFloatReg(reg_idx, val, width);
+ checkerTC->setFloatReg(reg_idx, val, width);
}
void setFloatReg(int reg_idx, FloatReg val)
{
- actualXC->setFloatReg(reg_idx, val);
- checkerXC->setFloatReg(reg_idx, val);
+ actualTC->setFloatReg(reg_idx, val);
+ checkerTC->setFloatReg(reg_idx, val);
}
void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{
- actualXC->setFloatRegBits(reg_idx, val, width);
- checkerXC->setFloatRegBits(reg_idx, val, width);
+ actualTC->setFloatRegBits(reg_idx, val, width);
+ checkerTC->setFloatRegBits(reg_idx, val, width);
}
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
- actualXC->setFloatRegBits(reg_idx, val);
- checkerXC->setFloatRegBits(reg_idx, val);
+ actualTC->setFloatRegBits(reg_idx, val);
+ checkerTC->setFloatRegBits(reg_idx, val);
}
- uint64_t readPC() { return actualXC->readPC(); }
+ uint64_t readPC() { return actualTC->readPC(); }
void setPC(uint64_t val)
{
- actualXC->setPC(val);
- checkerXC->setPC(val);
+ actualTC->setPC(val);
+ checkerTC->setPC(val);
checkerCPU->recordPCChange(val);
}
- uint64_t readNextPC() { return actualXC->readNextPC(); }
+ uint64_t readNextPC() { return actualTC->readNextPC(); }
void setNextPC(uint64_t val)
{
- actualXC->setNextPC(val);
- checkerXC->setNextPC(val);
+ actualTC->setNextPC(val);
+ checkerTC->setNextPC(val);
checkerCPU->recordNextPCChange(val);
}
- uint64_t readNextNPC() { return actualXC->readNextNPC(); }
+ uint64_t readNextNPC() { return actualTC->readNextNPC(); }
void setNextNPC(uint64_t val)
{
- actualXC->setNextNPC(val);
- checkerXC->setNextNPC(val);
+ actualTC->setNextNPC(val);
+ checkerTC->setNextNPC(val);
checkerCPU->recordNextPCChange(val);
}
MiscReg readMiscReg(int misc_reg)
- { return actualXC->readMiscReg(misc_reg); }
+ { return actualTC->readMiscReg(misc_reg); }
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
- { return actualXC->readMiscRegWithEffect(misc_reg, fault); }
+ { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
- checkerXC->setMiscReg(misc_reg, val);
- return actualXC->setMiscReg(misc_reg, val);
+ checkerTC->setMiscReg(misc_reg, val);
+ return actualTC->setMiscReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
- checkerXC->setMiscRegWithEffect(misc_reg, val);
- return actualXC->setMiscRegWithEffect(misc_reg, val);
+ checkerTC->setMiscRegWithEffect(misc_reg, val);
+ return actualTC->setMiscRegWithEffect(misc_reg, val);
}
unsigned readStCondFailures()
- { return actualXC->readStCondFailures(); }
+ { return actualTC->readStCondFailures(); }
void setStCondFailures(unsigned sc_failures)
{
- checkerXC->setStCondFailures(sc_failures);
- actualXC->setStCondFailures(sc_failures);
+ checkerTC->setStCondFailures(sc_failures);
+ actualTC->setStCondFailures(sc_failures);
}
#if FULL_SYSTEM
- bool inPalMode() { return actualXC->inPalMode(); }
+ bool inPalMode() { return actualTC->inPalMode(); }
#endif
// @todo: Fix this!
- bool misspeculating() { return actualXC->misspeculating(); }
+ bool misspeculating() { return actualTC->misspeculating(); }
#if !FULL_SYSTEM
- IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
+ IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
// used to shift args for indirect syscall
void setSyscallArg(int i, IntReg val)
{
- checkerXC->setSyscallArg(i, val);
- actualXC->setSyscallArg(i, val);
+ checkerTC->setSyscallArg(i, val);
+ actualTC->setSyscallArg(i, val);
}
void setSyscallReturn(SyscallReturn return_value)
{
- checkerXC->setSyscallReturn(return_value);
- actualXC->setSyscallReturn(return_value);
+ checkerTC->setSyscallReturn(return_value);
+ actualTC->setSyscallReturn(return_value);
}
- Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
+ Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
#endif
void changeRegFileContext(RegFile::ContextParam param,
RegFile::ContextVal val)
{
- actualXC->changeRegFileContext(param, val);
- checkerXC->changeRegFileContext(param, val);
+ actualTC->changeRegFileContext(param, val);
+ checkerTC->changeRegFileContext(param, val);
}
};