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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
commit25884a87733cd35ef6613aaef9a8a08194267552 (patch)
tree3eb831102c76206ba5ba4e19b94810be67ce108f /src/cpu/checker
parent32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (diff)
downloadgem5-25884a87733cd35ef6613aaef9a8a08194267552.tar.xz
Registers: Get rid of the float register width parameter.
Diffstat (limited to 'src/cpu/checker')
-rw-r--r--src/cpu/checker/cpu.hh36
-rw-r--r--src/cpu/checker/thread_context.hh18
2 files changed, 0 insertions, 54 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3b378700e..450ce6228 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -211,25 +211,12 @@ class CheckerCPU : public BaseCPU
return thread->readIntReg(si->srcRegIdx(idx));
}
- FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
- {
- int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return thread->readFloatReg(reg_idx, width);
- }
-
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx);
}
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
- int width)
- {
- int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return thread->readFloatRegBits(reg_idx, width);
- }
-
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
@@ -242,21 +229,6 @@ class CheckerCPU : public BaseCPU
result.integer = val;
}
- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
- int width)
- {
- int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- thread->setFloatReg(reg_idx, val, width);
- switch(width) {
- case 32:
- result.dbl = (double)val;
- break;
- case 64:
- result.dbl = val;
- break;
- };
- }
-
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
@@ -265,14 +237,6 @@ class CheckerCPU : public BaseCPU
}
void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
- {
- int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- thread->setFloatRegBits(reg_idx, val, width);
- result.integer = val;
- }
-
- void setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 2176c597a..d38bd2915 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -174,15 +174,9 @@ class CheckerThreadContext : public ThreadContext
uint64_t readIntReg(int reg_idx)
{ return actualTC->readIntReg(reg_idx); }
- FloatReg readFloatReg(int reg_idx, int width)
- { return actualTC->readFloatReg(reg_idx, width); }
-
FloatReg readFloatReg(int reg_idx)
{ return actualTC->readFloatReg(reg_idx); }
- FloatRegBits readFloatRegBits(int reg_idx, int width)
- { return actualTC->readFloatRegBits(reg_idx, width); }
-
FloatRegBits readFloatRegBits(int reg_idx)
{ return actualTC->readFloatRegBits(reg_idx); }
@@ -192,24 +186,12 @@ class CheckerThreadContext : public ThreadContext
checkerTC->setIntReg(reg_idx, val);
}
- void setFloatReg(int reg_idx, FloatReg val, int width)
- {
- actualTC->setFloatReg(reg_idx, val, width);
- checkerTC->setFloatReg(reg_idx, val, width);
- }
-
void setFloatReg(int reg_idx, FloatReg val)
{
actualTC->setFloatReg(reg_idx, val);
checkerTC->setFloatReg(reg_idx, val);
}
- void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
- {
- actualTC->setFloatRegBits(reg_idx, val, width);
- checkerTC->setFloatRegBits(reg_idx, val, width);
- }
-
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
actualTC->setFloatRegBits(reg_idx, val);