ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.

This change modifies the way prefetches work. They are now like normal loads
that don't writeback a register. Previously prefetches were supposed to call
prefetch() on the exection context, so they executed with execute() methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs
are blank, meaning that they get executed, but don't actually do anything.

On Alpha dead cache copy code was removed and prefetches are now normal ops.
They count as executed operations, but still don't do anything and IsMemRef is
not longer set on them.

On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch
instructions. The timing simple CPU doesn't try to do anything special for
prefetches now and they execute with the normal memory code path.

2 files changed, 0 insertions, 26 deletions

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 16b779e06..10dd77899 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -134,18 +134,6 @@ CheckerCPU::unserialize(Checkpoint *cp, const string &section)
 */
 }
 
-Fault
-CheckerCPU::copySrcTranslate(Addr src)
-{
-    panic("Unimplemented!");
-}
-
-Fault
-CheckerCPU::copy(Addr dest)
-{
-    panic("Unimplemented!");
-}
-
 template <class T>
 Fault
 CheckerCPU::read(Addr addr, T &data, unsigned flags)
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index df5d8209b..efd8a4776 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -178,20 +178,6 @@ class CheckerCPU : public BaseCPU
     void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
     Addr getEA()        { panic("SimpleCPU::getEA() not implemented\n"); }
 
-    void prefetch(Addr addr, unsigned flags)
-    {
-        // need to do this...
-    }
-
-    void writeHint(Addr addr, int size, unsigned flags)
-    {
-        // need to do this...
-    }
-
-    Fault copySrcTranslate(Addr src);
-
-    Fault copy(Addr dest);
-
     // The register accessor methods provide the index of the
     // instruction's operand (e.g., 0 or 1), not the architectural
     // register index, to simplify the implementation of register