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authorTuan Ta <qtt2@cornell.edu>2018-01-22 13:12:50 -0500
committerTuan Ta <qtt2@cornell.edu>2019-02-08 15:27:04 +0000
commit25dc765889d948693995cfa622f001aa94b5364b (patch)
tree38a8e93881ad150a482020a1fd706d664ee0c061 /src/cpu/checker
parent165a7dab558c8118622a387683521bea1ebf2e6c (diff)
downloadgem5-25dc765889d948693995cfa622f001aa94b5364b.tar.xz
cpu: support atomic memory request type with AtomicOpFunctor
This patch enables all 4 CPU models (AtomicSimpleCPU, TimingSimpleCPU, MinorCPU and DerivO3CPU) to issue atomic memory (AMO) requests to memory system. Atomic memory instruction is treated as a special store instruction in all CPU models. In simple CPUs, an AMO request with an associated AtomicOpFunctor is simply sent to L1 dcache. In MinorCPU, an AMO request bypasses store buffer and waits for any conflicting store request(s) currently in the store buffer to retire before the AMO request is sent to the cache. AMO requests are not buffered in the store buffer, so their effects appear immediately in the cache. In DerivO3CPU, an AMO request is inserted in the store buffer so that it is delivered to the cache only after all previous stores are issued to the cache. Data forwarding between between an outstanding AMO in the store buffer and a subsequent load is not allowed since the AMO request does not hold valid data until it's executed in the cache. This implementation assumes that a target ISA implementation must insert enough memory fences as micro-ops around an atomic instruction to enforce a correct order of memory instructions with respect to its memory consistency model. Without extra memory fences, this implementation can allow AMOs and other memory instructions that do not conflict (i.e., not target the same address) to reorder. This implementation also assumes that atomic instructions execute within a cache line boundary since the cache for now is not able to execute an operation on two different cache lines in one single step. Therefore, ISAs like x86 that require multi-cache-line atomic instructions need to either use a pair of locking load and unlocking store or change the cache implementation to guarantee the atomicity of an atomic instruction. Change-Id: Ib8a7c81868ac05b98d73afc7d16eb88486f8cf9a Reviewed-on: https://gem5-review.googlesource.com/c/8188 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/checker')
-rw-r--r--src/cpu/checker/cpu.hh7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index e32c015bf..5f830d7a9 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -536,9 +536,16 @@ class CheckerCPU : public BaseCPU, public ExecContext
Fault readMem(Addr addr, uint8_t *data, unsigned size,
Request::Flags flags) override;
+
Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res) override;
+ Fault amoMem(Addr addr, uint8_t* data, unsigned size,
+ Request::Flags flags, AtomicOpFunctor *amo_op) override
+ {
+ panic("AMO is not supported yet in CPU checker\n");
+ }
+
unsigned int
readStCondFailures() const override {
return thread->readStCondFailures();