arch: cpu: Rename *FloatRegBits* to *FloatReg*.

Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.

Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

3 files changed, 14 insertions, 14 deletions

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 9d6061ad8..30d17bdf6 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -199,7 +199,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     {
         const RegId& reg = si->srcRegIdx(idx);
         assert(reg.isFloatReg());
-        return thread->readFloatRegBits(reg.index());
+        return thread->readFloatReg(reg.index());
     }
 
     /**
@@ -374,7 +374,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isFloatReg());
-        thread->setFloatRegBits(reg.index(), val);
+        thread->setFloatReg(reg.index(), val);
         setScalarResult(val);
     }
 
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index f6c35439b..86f022d41 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -208,7 +208,7 @@ Checker<Impl>::verify(const DynInstPtr &completed_inst)
         // maintain $r0 semantics
         thread->setIntReg(ZeroReg, 0);
 #if THE_ISA == ALPHA_ISA
-        thread->setFloatRegBits(ZeroReg, 0);
+        thread->setFloatReg(ZeroReg, 0);
 #endif
 
         // Check if any recent PC changes match up with anything we
@@ -609,7 +609,7 @@ Checker<Impl>::copyResult(const DynInstPtr &inst,
             break;
           case FloatRegClass:
             panic_if(!mismatch_val.isScalar(), "Unexpected type of result");
-            thread->setFloatRegBits(idx.index(), mismatch_val.asInteger());
+            thread->setFloatReg(idx.index(), mismatch_val.asInteger());
             break;
           case VecRegClass:
             panic_if(!mismatch_val.isVector(), "Unexpected type of result");
@@ -644,7 +644,7 @@ Checker<Impl>::copyResult(const DynInstPtr &inst,
             break;
           case FloatRegClass:
             panic_if(!res.isScalar(), "Unexpected type of result");
-            thread->setFloatRegBits(idx.index(), res.asInteger());
+            thread->setFloatReg(idx.index(), res.asInteger());
             break;
           case VecRegClass:
             panic_if(!res.isVector(), "Unexpected type of result");
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 8ce5a740d..99506c1c8 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -209,9 +209,9 @@ class CheckerThreadContext : public ThreadContext
     RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
 
     RegVal
-    readFloatRegBits(int reg_idx)
+    readFloatReg(int reg_idx)
     {
-        return actualTC->readFloatRegBits(reg_idx);
+        return actualTC->readFloatReg(reg_idx);
     }
 
     const VecRegContainer& readVecReg(const RegId& reg) const
@@ -280,10 +280,10 @@ class CheckerThreadContext : public ThreadContext
     }
 
     void
-    setFloatRegBits(int reg_idx, RegVal val)
+    setFloatReg(int reg_idx, RegVal val)
     {
-        actualTC->setFloatRegBits(reg_idx, val);
-        checkerTC->setFloatRegBits(reg_idx, val);
+        actualTC->setFloatReg(reg_idx, val);
+        checkerTC->setFloatReg(reg_idx, val);
     }
 
     void
@@ -404,15 +404,15 @@ class CheckerThreadContext : public ThreadContext
     }
 
     RegVal
-    readFloatRegBitsFlat(int idx)
+    readFloatRegFlat(int idx)
     {
-        return actualTC->readFloatRegBitsFlat(idx);
+        return actualTC->readFloatRegFlat(idx);
     }
 
     void
-    setFloatRegBitsFlat(int idx, RegVal val)
+    setFloatRegFlat(int idx, RegVal val)
     {
-        actualTC->setFloatRegBitsFlat(idx, val);
+        actualTC->setFloatRegFlat(idx, val);
     }
 
     const VecRegContainer &