cpu: Eliminate the ProxyThreadContext class.

Replace it with direct inheritance from the ThreadContext class in the
SimpleThread class which was the only place it was used.

Also take the opportunity to use some specialized types instead of
ints, etc., add some consts, and fix some style issues.

Change-Id: I5d2cfa87b20dc43615e33e6755c9d016564e9c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18048
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

1 files changed, 206 insertions, 105 deletions

diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index d88c9b250..26973cdbf 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -98,7 +98,8 @@ class CheckerThreadContext : public ThreadContext
 
     ContextID contextId() const override { return actualTC->contextId(); }
 
-    void setContextId(ContextID id)override
+    void
+    setContextId(ContextID id) override
     {
        actualTC->setContextId(id);
        checkerTC->setContextId(id);
@@ -106,7 +107,8 @@ class CheckerThreadContext : public ThreadContext
 
     /** Returns this thread's ID number. */
     int threadId() const override { return actualTC->threadId(); }
-    void setThreadId(int id) override
+    void
+    setThreadId(int id) override
     {
         checkerTC->setThreadId(id);
         actualTC->setThreadId(id);
@@ -116,21 +118,27 @@ class CheckerThreadContext : public ThreadContext
 
     BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
 
-    CheckerCPU *getCheckerCpuPtr()override
+    CheckerCPU *
+    getCheckerCpuPtr() override
     {
         return checkerCPU;
     }
 
     TheISA::ISA *getIsaPtr() override { return actualTC->getIsaPtr(); }
 
-    TheISA::Decoder *getDecoderPtr() override {
+    TheISA::Decoder *
+    getDecoderPtr() override
+    {
         return actualTC->getDecoderPtr();
     }
 
     System *getSystemPtr() override { return actualTC->getSystemPtr(); }
 
-    TheISA::Kernel::Statistics *getKernelStats()override
-    { return actualTC->getKernelStats(); }
+    TheISA::Kernel::Statistics *
+    getKernelStats() override
+    {
+        return actualTC->getKernelStats();
+    }
 
     Process *getProcessPtr() override { return actualTC->getProcessPtr(); }
 
@@ -138,28 +146,41 @@ class CheckerThreadContext : public ThreadContext
 
     PortProxy &getPhysProxy() override { return actualTC->getPhysProxy(); }
 
-    FSTranslatingPortProxy &getVirtProxy() override
-    { return actualTC->getVirtProxy(); }
+    FSTranslatingPortProxy &
+    getVirtProxy() override
+    {
+        return actualTC->getVirtProxy();
+    }
 
-    void initMemProxies(ThreadContext *tc) override
-    { actualTC->initMemProxies(tc); }
+    void
+    initMemProxies(ThreadContext *tc) override
+    {
+        actualTC->initMemProxies(tc);
+    }
 
-    void connectMemPorts(ThreadContext *tc)
+    void
+    connectMemPorts(ThreadContext *tc)
     {
         actualTC->connectMemPorts(tc);
     }
 
-    SETranslatingPortProxy &getMemProxy() override {
+    SETranslatingPortProxy &
+    getMemProxy() override
+    {
         return actualTC->getMemProxy();
     }
 
     /** Executes a syscall in SE mode. */
-    void syscall(int64_t callnum, Fault *fault)override
-    { return actualTC->syscall(callnum, fault); }
+    void
+    syscall(int64_t callnum, Fault *fault) override
+    {
+        return actualTC->syscall(callnum, fault);
+    }
 
     Status status() const override { return actualTC->status(); }
 
-    void setStatus(Status new_status) override
+    void
+    setStatus(Status new_status) override
     {
         actualTC->setStatus(new_status);
         checkerTC->setStatus(new_status);
@@ -169,43 +190,49 @@ class CheckerThreadContext : public ThreadContext
     void activate() override { actualTC->activate(); }
 
     /// Set the status to Suspended.
-    void suspend() override{ actualTC->suspend(); }
+    void suspend() override { actualTC->suspend(); }
 
     /// Set the status to Halted.
-    void halt() override{ actualTC->halt(); }
+    void halt() override { actualTC->halt(); }
 
-    void dumpFuncProfile()  override{ actualTC->dumpFuncProfile(); }
+    void dumpFuncProfile() override { actualTC->dumpFuncProfile(); }
 
-    void takeOverFrom(ThreadContext *oldContext) override
+    void
+    takeOverFrom(ThreadContext *oldContext) override
     {
         actualTC->takeOverFrom(oldContext);
         checkerTC->copyState(oldContext);
     }
 
-    void regStats(const std::string &name) override
+    void
+    regStats(const std::string &name) override
     {
         actualTC->regStats(name);
         checkerTC->regStats(name);
     }
 
-    EndQuiesceEvent *getQuiesceEvent() override {
+    EndQuiesceEvent *
+    getQuiesceEvent() override
+    {
         return actualTC->getQuiesceEvent();
     }
 
-    Tick readLastActivate()  override{ return actualTC->readLastActivate(); }
-    Tick readLastSuspend()  override{ return actualTC->readLastSuspend(); }
+    Tick readLastActivate() override { return actualTC->readLastActivate(); }
+    Tick readLastSuspend() override { return actualTC->readLastSuspend(); }
 
-    void profileClear()  override{ return actualTC->profileClear(); }
-    void profileSample()  override{ return actualTC->profileSample(); }
+    void profileClear() override { return actualTC->profileClear(); }
+    void profileSample() override { return actualTC->profileSample(); }
 
     // @todo: Do I need this?
-    void copyArchRegs(ThreadContext *tc) override
+    void
+    copyArchRegs(ThreadContext *tc) override
     {
         actualTC->copyArchRegs(tc);
         checkerTC->copyArchRegs(tc);
     }
 
-    void clearArchRegs() override
+    void
+    clearArchRegs() override
     {
         actualTC->clearArchRegs();
         checkerTC->clearArchRegs();
@@ -214,83 +241,123 @@ class CheckerThreadContext : public ThreadContext
     //
     // New accessors for new decoder.
     //
-    RegVal readIntReg(int reg_idx) override {
+    RegVal
+    readIntReg(RegIndex reg_idx) const override
+    {
         return actualTC->readIntReg(reg_idx);
     }
 
     RegVal
-    readFloatReg(int reg_idx) override
+    readFloatReg(RegIndex reg_idx) const override
     {
         return actualTC->readFloatReg(reg_idx);
     }
 
-    const VecRegContainer& readVecReg (const RegId& reg) const override
-    { return actualTC->readVecReg(reg); }
+    const VecRegContainer &
+    readVecReg (const RegId &reg) const override
+    {
+        return actualTC->readVecReg(reg);
+    }
 
     /**
      * Read vector register for modification, hierarchical indexing.
      */
-    VecRegContainer& getWritableVecReg (const RegId& reg) override
-    { return actualTC->getWritableVecReg(reg); }
+    VecRegContainer &
+    getWritableVecReg (const RegId &reg) override
+    {
+        return actualTC->getWritableVecReg(reg);
+    }
 
     /** Vector Register Lane Interfaces. */
     /** @{ */
     /** Reads source vector 8bit operand. */
     ConstVecLane8
-    readVec8BitLaneReg(const RegId& reg) const override
-    { return actualTC->readVec8BitLaneReg(reg); }
+    readVec8BitLaneReg(const RegId &reg) const override
+    {
+        return actualTC->readVec8BitLaneReg(reg);
+    }
 
     /** Reads source vector 16bit operand. */
     ConstVecLane16
-    readVec16BitLaneReg(const RegId& reg) const override
-    { return actualTC->readVec16BitLaneReg(reg); }
+    readVec16BitLaneReg(const RegId &reg) const override
+    {
+        return actualTC->readVec16BitLaneReg(reg);
+    }
 
     /** Reads source vector 32bit operand. */
     ConstVecLane32
-    readVec32BitLaneReg(const RegId& reg) const override
-    { return actualTC->readVec32BitLaneReg(reg); }
+    readVec32BitLaneReg(const RegId &reg) const override
+    {
+        return actualTC->readVec32BitLaneReg(reg);
+    }
 
     /** Reads source vector 64bit operand. */
     ConstVecLane64
-    readVec64BitLaneReg(const RegId& reg) const override
-    { return actualTC->readVec64BitLaneReg(reg); }
+    readVec64BitLaneReg(const RegId &reg) const override
+    {
+        return actualTC->readVec64BitLaneReg(reg);
+    }
 
     /** Write a lane of the destination vector register. */
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::Byte>& val) override
-    { return actualTC->setVecLane(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::TwoByte>& val) override
-    { return actualTC->setVecLane(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::FourByte>& val) override
-    { return actualTC->setVecLane(reg, val); }
-    virtual void setVecLane(const RegId& reg,
-            const LaneData<LaneSize::EightByte>& val) override
-    { return actualTC->setVecLane(reg, val); }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::Byte> &val) override
+    {
+        return actualTC->setVecLane(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::TwoByte> &val) override
+    {
+        return actualTC->setVecLane(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::FourByte> &val) override
+    {
+        return actualTC->setVecLane(reg, val);
+    }
+    virtual void
+    setVecLane(const RegId &reg,
+               const LaneData<LaneSize::EightByte> &val) override
+    {
+        return actualTC->setVecLane(reg, val);
+    }
     /** @} */
 
-    const VecElem& readVecElem(const RegId& reg) const override
-    { return actualTC->readVecElem(reg); }
+    const VecElem &
+    readVecElem(const RegId& reg) const override
+    {
+        return actualTC->readVecElem(reg);
+    }
 
-    const VecPredRegContainer& readVecPredReg(const RegId& reg) const override
-    { return actualTC->readVecPredReg(reg); }
+    const VecPredRegContainer &
+    readVecPredReg(const RegId& reg) const override
+    {
+        return actualTC->readVecPredReg(reg);
+    }
 
-    VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override
-    { return actualTC->getWritableVecPredReg(reg); }
+    VecPredRegContainer &
+    getWritableVecPredReg(const RegId& reg) override
+    {
+        return actualTC->getWritableVecPredReg(reg);
+    }
 
-    RegVal readCCReg(int reg_idx) override
-    { return actualTC->readCCReg(reg_idx); }
+    RegVal
+    readCCReg(RegIndex reg_idx) const override
+    {
+        return actualTC->readCCReg(reg_idx);
+    }
 
     void
-    setIntReg(int reg_idx, RegVal val) override
+    setIntReg(RegIndex reg_idx, RegVal val) override
     {
         actualTC->setIntReg(reg_idx, val);
         checkerTC->setIntReg(reg_idx, val);
     }
 
     void
-    setFloatReg(int reg_idx, RegVal val) override
+    setFloatReg(RegIndex reg_idx, RegVal val) override
     {
         actualTC->setFloatReg(reg_idx, val);
         checkerTC->setFloatReg(reg_idx, val);
@@ -318,15 +385,14 @@ class CheckerThreadContext : public ThreadContext
     }
 
     void
-    setCCReg(int reg_idx, RegVal val) override
+    setCCReg(RegIndex reg_idx, RegVal val) override
     {
         actualTC->setCCReg(reg_idx, val);
         checkerTC->setCCReg(reg_idx, val);
     }
 
     /** Reads this thread's PC state. */
-    TheISA::PCState pcState() override
-    { return actualTC->pcState(); }
+    TheISA::PCState pcState() const override { return actualTC->pcState(); }
 
     /** Sets this thread's PC state. */
     void
@@ -353,25 +419,28 @@ class CheckerThreadContext : public ThreadContext
     }
 
     /** Reads this thread's PC. */
-    Addr instAddr() override
-    { return actualTC->instAddr(); }
+    Addr instAddr() const override { return actualTC->instAddr(); }
 
     /** Reads this thread's next PC. */
-    Addr nextInstAddr() override
-    { return actualTC->nextInstAddr(); }
+    Addr nextInstAddr() const override { return actualTC->nextInstAddr(); }
 
     /** Reads this thread's next PC. */
-    MicroPC microPC() override
-    { return actualTC->microPC(); }
+    MicroPC microPC() const override { return actualTC->microPC(); }
 
-    RegVal readMiscRegNoEffect(int misc_reg) const override
-    { return actualTC->readMiscRegNoEffect(misc_reg); }
+    RegVal
+    readMiscRegNoEffect(RegIndex misc_reg) const override
+    {
+        return actualTC->readMiscRegNoEffect(misc_reg);
+    }
 
-    RegVal readMiscReg(int misc_reg) override
-    { return actualTC->readMiscReg(misc_reg); }
+    RegVal
+    readMiscReg(RegIndex misc_reg) override
+    {
+        return actualTC->readMiscReg(misc_reg);
+    }
 
     void
-    setMiscRegNoEffect(int misc_reg, RegVal val) override
+    setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
     {
         DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
                          " and O3..\n", misc_reg);
@@ -380,7 +449,7 @@ class CheckerThreadContext : public ThreadContext
     }
 
     void
-    setMiscReg(int misc_reg, RegVal val) override
+    setMiscReg(RegIndex misc_reg, RegVal val) override
     {
         DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
                          " and O3..\n", misc_reg);
@@ -394,8 +463,11 @@ class CheckerThreadContext : public ThreadContext
         return actualTC->flattenRegId(regId);
     }
 
-    unsigned readStCondFailures() override
-    { return actualTC->readStCondFailures(); }
+    unsigned
+    readStCondFailures() const override
+    {
+        return actualTC->readStCondFailures();
+    }
 
     void
     setStCondFailures(unsigned sc_failures) override
@@ -403,32 +475,38 @@ class CheckerThreadContext : public ThreadContext
         actualTC->setStCondFailures(sc_failures);
     }
 
-    Counter readFuncExeInst() override { return actualTC->readFuncExeInst(); }
+    Counter
+    readFuncExeInst() const override
+    {
+        return actualTC->readFuncExeInst();
+    }
 
-    RegVal readIntRegFlat(int idx) override {
+    RegVal
+    readIntRegFlat(RegIndex idx) const override
+    {
         return actualTC->readIntRegFlat(idx);
     }
 
     void
-    setIntRegFlat(int idx, RegVal val) override
+    setIntRegFlat(RegIndex idx, RegVal val) override
     {
         actualTC->setIntRegFlat(idx, val);
     }
 
     RegVal
-    readFloatRegFlat(int idx) override
+    readFloatRegFlat(RegIndex idx) const override
     {
         return actualTC->readFloatRegFlat(idx);
     }
 
     void
-    setFloatRegFlat(int idx, RegVal val) override
+    setFloatRegFlat(RegIndex idx, RegVal val) override
     {
         actualTC->setFloatRegFlat(idx, val);
     }
 
     const VecRegContainer &
-    readVecRegFlat(int idx) const override
+    readVecRegFlat(RegIndex idx) const override
     {
         return actualTC->readVecRegFlat(idx);
     }
@@ -437,36 +515,59 @@ class CheckerThreadContext : public ThreadContext
      * Read vector register for modification, flat indexing.
      */
     VecRegContainer &
-    getWritableVecRegFlat(int idx) override
+    getWritableVecRegFlat(RegIndex idx) override
     {
         return actualTC->getWritableVecRegFlat(idx);
     }
 
-    void setVecRegFlat(int idx, const VecRegContainer& val) override
-    { actualTC->setVecRegFlat(idx, val); }
+    void
+    setVecRegFlat(RegIndex idx, const VecRegContainer& val) override
+    {
+        actualTC->setVecRegFlat(idx, val);
+    }
 
-    const VecElem& readVecElemFlat(const RegIndex& idx,
-                                   const ElemIndex& elem_idx) const override
-    { return actualTC->readVecElemFlat(idx, elem_idx); }
+    const VecElem &
+    readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
+    {
+        return actualTC->readVecElemFlat(idx, elem_idx);
+    }
 
-    void setVecElemFlat(const RegIndex& idx,
-                        const ElemIndex& elem_idx, const VecElem& val) override
-    { actualTC->setVecElemFlat(idx, elem_idx, val); }
+    void
+    setVecElemFlat(RegIndex idx,
+                   const ElemIndex& elem_idx, const VecElem& val) override
+    {
+        actualTC->setVecElemFlat(idx, elem_idx, val);
+    }
 
-    const VecPredRegContainer& readVecPredRegFlat(int idx) const override
-    { return actualTC->readVecPredRegFlat(idx); }
+    const VecPredRegContainer &
+    readVecPredRegFlat(RegIndex idx) const override
+    {
+        return actualTC->readVecPredRegFlat(idx);
+    }
 
-    VecPredRegContainer& getWritableVecPredRegFlat(int idx) override
-    { return actualTC->getWritableVecPredRegFlat(idx); }
+    VecPredRegContainer &
+    getWritableVecPredRegFlat(RegIndex idx) override
+    {
+        return actualTC->getWritableVecPredRegFlat(idx);
+    }
 
-    void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override
-    { actualTC->setVecPredRegFlat(idx, val); }
+    void
+    setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override
+    {
+        actualTC->setVecPredRegFlat(idx, val);
+    }
 
-    RegVal readCCRegFlat(int idx) override
-    { return actualTC->readCCRegFlat(idx); }
+    RegVal
+    readCCRegFlat(RegIndex idx) const override
+    {
+        return actualTC->readCCRegFlat(idx);
+    }
 
-    void setCCRegFlat(int idx, RegVal val) override
-    { actualTC->setCCRegFlat(idx, val); }
+    void
+    setCCRegFlat(RegIndex idx, RegVal val) override
+    {
+        actualTC->setCCRegFlat(idx, val);
+    }
 };
 
 #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__