diff options
author | Gabe Black <gabeblack@google.com> | 2018-11-19 17:20:31 -0800 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2018-12-20 19:27:51 +0000 |
commit | 88bbabe93f339f9db301caf43bf2cca2a0e8048c (patch) | |
tree | 66323afaa9348f392deafe11d88973fd3034001b /src/cpu/checker | |
parent | 67d58e81825d7dff17def2cfeedf5d958141be55 (diff) | |
download | gem5-88bbabe93f339f9db301caf43bf2cca2a0e8048c.tar.xz |
arch, cpu: Remove float type accessors.
Use the binary accessors instead.
Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2
Reviewed-on: https://gem5-review.googlesource.com/c/14457
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/checker')
-rw-r--r-- | src/cpu/checker/cpu.hh | 16 | ||||
-rw-r--r-- | src/cpu/checker/cpu_impl.hh | 2 | ||||
-rw-r--r-- | src/cpu/checker/thread_context.hh | 15 |
3 files changed, 1 insertions, 32 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index cb87f622a..5673641aa 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -196,13 +196,6 @@ class CheckerCPU : public BaseCPU, public ExecContext return thread->readIntReg(reg.index()); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) override - { - const RegId& reg = si->srcRegIdx(idx); - assert(reg.isFloatReg()); - return thread->readFloatReg(reg.index()); - } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override { @@ -353,15 +346,6 @@ class CheckerCPU : public BaseCPU, public ExecContext setScalarResult(val); } - void setFloatRegOperand(const StaticInst *si, int idx, - FloatReg val) override - { - const RegId& reg = si->destRegIdx(idx); - assert(reg.isFloatReg()); - thread->setFloatReg(reg.index(), val); - setScalarResult(val); - } - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) override { diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 4fa59564a..f6c35439b 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -208,7 +208,7 @@ Checker<Impl>::verify(const DynInstPtr &completed_inst) // maintain $r0 semantics thread->setIntReg(ZeroReg, 0); #if THE_ISA == ALPHA_ISA - thread->setFloatReg(ZeroReg, 0.0); + thread->setFloatRegBits(ZeroReg, 0); #endif // Check if any recent PC changes match up with anything we diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 975bd9f96..85053dfa6 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -209,9 +209,6 @@ class CheckerThreadContext : public ThreadContext uint64_t readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); } - FloatReg readFloatReg(int reg_idx) - { return actualTC->readFloatReg(reg_idx); } - FloatRegBits readFloatRegBits(int reg_idx) { return actualTC->readFloatRegBits(reg_idx); } @@ -273,12 +270,6 @@ class CheckerThreadContext : public ThreadContext checkerTC->setIntReg(reg_idx, val); } - void setFloatReg(int reg_idx, FloatReg val) - { - actualTC->setFloatReg(reg_idx, val); - checkerTC->setFloatReg(reg_idx, val); - } - void setFloatRegBits(int reg_idx, FloatRegBits val) { actualTC->setFloatRegBits(reg_idx, val); @@ -382,12 +373,6 @@ class CheckerThreadContext : public ThreadContext void setIntRegFlat(int idx, uint64_t val) { actualTC->setIntRegFlat(idx, val); } - FloatReg readFloatRegFlat(int idx) - { return actualTC->readFloatRegFlat(idx); } - - void setFloatRegFlat(int idx, FloatReg val) - { actualTC->setFloatRegFlat(idx, val); } - FloatRegBits readFloatRegBitsFlat(int idx) { return actualTC->readFloatRegBitsFlat(idx); } |