cpu: dev: sim: gpu-compute: Banish some ISA specific register types.

These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.

Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

2 files changed, 135 insertions, 89 deletions

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 5673641aa..2c7e022bd 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -88,9 +88,6 @@ class CheckerCPU : public BaseCPU, public ExecContext
 {
   protected:
     typedef TheISA::MachInst MachInst;
-    typedef TheISA::FloatReg FloatReg;
-    typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscReg MiscReg;
     using VecRegContainer = TheISA::VecRegContainer;
 
     /** id attached to all issued requests */
@@ -189,15 +186,16 @@ class CheckerCPU : public BaseCPU, public ExecContext
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    IntReg readIntRegOperand(const StaticInst *si, int idx) override
+    RegVal
+    readIntRegOperand(const StaticInst *si, int idx) override
     {
         const RegId& reg = si->srcRegIdx(idx);
         assert(reg.isIntReg());
         return thread->readIntReg(reg.index());
     }
 
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si,
-                                         int idx) override
+    RegVal
+    readFloatRegOperandBits(const StaticInst *si, int idx) override
     {
         const RegId& reg = si->srcRegIdx(idx);
         assert(reg.isFloatReg());
@@ -207,8 +205,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
     /**
      * Read source vector register operand.
      */
-    const VecRegContainer& readVecRegOperand(const StaticInst *si,
-                                             int idx) const override
+    const VecRegContainer &
+    readVecRegOperand(const StaticInst *si, int idx) const override
     {
         const RegId& reg = si->srcRegIdx(idx);
         assert(reg.isVecReg());
@@ -218,8 +216,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
     /**
      * Read destination vector register operand for modification.
      */
-    VecRegContainer& getWritableVecRegOperand(const StaticInst *si,
-                                             int idx) override
+    VecRegContainer &
+    getWritableVecRegOperand(const StaticInst *si, int idx) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isVecReg());
@@ -230,8 +228,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     /** @{ */
     /** Reads source vector 8bit operand. */
     virtual ConstVecLane8
-    readVec8BitLaneOperand(const StaticInst *si, int idx) const
-                            override
+    readVec8BitLaneOperand(const StaticInst *si, int idx) const override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isVecReg());
@@ -240,8 +237,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
 
     /** Reads source vector 16bit operand. */
     virtual ConstVecLane16
-    readVec16BitLaneOperand(const StaticInst *si, int idx) const
-                            override
+    readVec16BitLaneOperand(const StaticInst *si, int idx) const override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isVecReg());
@@ -250,8 +246,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
 
     /** Reads source vector 32bit operand. */
     virtual ConstVecLane32
-    readVec32BitLaneOperand(const StaticInst *si, int idx) const
-                            override
+    readVec32BitLaneOperand(const StaticInst *si, int idx) const override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isVecReg());
@@ -260,8 +255,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
 
     /** Reads source vector 64bit operand. */
     virtual ConstVecLane64
-    readVec64BitLaneOperand(const StaticInst *si, int idx) const
-                            override
+    readVec64BitLaneOperand(const StaticInst *si, int idx) const override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isVecReg());
@@ -303,13 +297,15 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
     /** @} */
 
-    VecElem readVecElemOperand(const StaticInst *si, int idx) const override
+    VecElem
+    readVecElemOperand(const StaticInst *si, int idx) const override
     {
         const RegId& reg = si->srcRegIdx(idx);
         return thread->readVecElem(reg);
     }
 
-    CCReg readCCRegOperand(const StaticInst *si, int idx) override
+    CCReg
+    readCCRegOperand(const StaticInst *si, int idx) override
     {
         const RegId& reg = si->srcRegIdx(idx);
         assert(reg.isCCReg());
@@ -317,28 +313,31 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
 
     template<typename T>
-    void setScalarResult(T&& t)
+    void
+    setScalarResult(T&& t)
     {
         result.push(InstResult(std::forward<T>(t),
-                        InstResult::ResultType::Scalar));
+                               InstResult::ResultType::Scalar));
     }
 
     template<typename T>
-    void setVecResult(T&& t)
+    void
+    setVecResult(T&& t)
     {
         result.push(InstResult(std::forward<T>(t),
-                        InstResult::ResultType::VecReg));
+                               InstResult::ResultType::VecReg));
     }
 
     template<typename T>
-    void setVecElemResult(T&& t)
+    void
+    setVecElemResult(T&& t)
     {
         result.push(InstResult(std::forward<T>(t),
-                        InstResult::ResultType::VecElem));
+                               InstResult::ResultType::VecElem));
     }
 
-    void setIntRegOperand(const StaticInst *si, int idx,
-                          IntReg val) override
+    void
+    setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isIntReg());
@@ -346,8 +345,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
         setScalarResult(val);
     }
 
-    void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val) override
+    void
+    setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isFloatReg());
@@ -355,7 +354,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
         setScalarResult(val);
     }
 
-    void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+    void
+    setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isCCReg());
@@ -363,8 +363,9 @@ class CheckerCPU : public BaseCPU, public ExecContext
         setScalarResult((uint64_t)val);
     }
 
-    void setVecRegOperand(const StaticInst *si, int idx,
-                                const VecRegContainer& val) override
+    void
+    setVecRegOperand(const StaticInst *si, int idx,
+                     const VecRegContainer& val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isVecReg());
@@ -372,8 +373,9 @@ class CheckerCPU : public BaseCPU, public ExecContext
         setVecResult(val);
     }
 
-    void setVecElemOperand(const StaticInst *si, int idx,
-                           const VecElem val) override
+    void
+    setVecElemOperand(const StaticInst *si, int idx,
+                      const VecElem val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isVecElem());
@@ -383,13 +385,15 @@ class CheckerCPU : public BaseCPU, public ExecContext
 
     bool readPredicate() const override { return thread->readPredicate(); }
 
-    void setPredicate(bool val) override
+    void
+    setPredicate(bool val) override
     {
         thread->setPredicate(val);
     }
 
     TheISA::PCState pcState() const override { return thread->pcState(); }
-    void pcState(const TheISA::PCState &val) override
+    void
+    pcState(const TheISA::PCState &val) override
     {
         DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
                          val, thread->pcState());
@@ -400,39 +404,47 @@ class CheckerCPU : public BaseCPU, public ExecContext
     MicroPC microPC() { return thread->microPC(); }
     //////////////////////////////////////////
 
-    MiscReg readMiscRegNoEffect(int misc_reg) const
+    RegVal
+    readMiscRegNoEffect(int misc_reg) const
     {
         return thread->readMiscRegNoEffect(misc_reg);
     }
 
-    MiscReg readMiscReg(int misc_reg) override
+    RegVal
+    readMiscReg(int misc_reg) override
     {
         return thread->readMiscReg(misc_reg);
     }
 
-    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+    void
+    setMiscRegNoEffect(int misc_reg, const RegVal &val)
     {
-        DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg);
+        DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
+                misc_reg);
         miscRegIdxs.push(misc_reg);
         return thread->setMiscRegNoEffect(misc_reg, val);
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val) override
+    void
+    setMiscReg(int misc_reg, const RegVal &val) override
     {
-        DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
+        DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
+                misc_reg);
         miscRegIdxs.push(misc_reg);
         return thread->setMiscReg(misc_reg, val);
     }
 
-    MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
+    RegVal
+    readMiscRegOperand(const StaticInst *si, int idx) override
     {
         const RegId& reg = si->srcRegIdx(idx);
         assert(reg.isMiscReg());
         return thread->readMiscReg(reg.index());
     }
 
-    void setMiscRegOperand(const StaticInst *si, int idx,
-                           const MiscReg &val) override
+    void
+    setMiscRegOperand(const StaticInst *si, int idx,
+                      const RegVal &val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isMiscReg());
@@ -440,14 +452,15 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
 
 #if THE_ISA == MIPS_ISA
-    MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override
+    RegVal
+    readRegOtherThread(const RegId &misc_reg, ThreadID tid) override
     {
         panic("MIPS MT not defined for CheckerCPU.\n");
         return 0;
     }
 
-    void setRegOtherThread(const RegId& misc_reg, MiscReg val,
-                               ThreadID tid) override
+    void
+    setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override
     {
         panic("MIPS MT not defined for CheckerCPU.\n");
     }
@@ -455,33 +468,36 @@ class CheckerCPU : public BaseCPU, public ExecContext
 
     /////////////////////////////////////////
 
-    void recordPCChange(const TheISA::PCState &val)
+    void
+    recordPCChange(const TheISA::PCState &val)
     {
        changedPC = true;
        newPCState = val;
     }
 
-    void demapPage(Addr vaddr, uint64_t asn) override
+    void
+    demapPage(Addr vaddr, uint64_t asn) override
     {
         this->itb->demapPage(vaddr, asn);
         this->dtb->demapPage(vaddr, asn);
     }
 
     // monitor/mwait funtions
-    void armMonitor(Addr address) override
-    { BaseCPU::armMonitor(0, address); }
+    void armMonitor(Addr address) override { BaseCPU::armMonitor(0, address); }
     bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
     void mwaitAtomic(ThreadContext *tc) override
     { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
     AddressMonitor *getAddrMonitor() override
     { return BaseCPU::getCpuAddrMonitor(0); }
 
-    void demapInstPage(Addr vaddr, uint64_t asn)
+    void
+    demapInstPage(Addr vaddr, uint64_t asn)
     {
         this->itb->demapPage(vaddr, asn);
     }
 
-    void demapDataPage(Addr vaddr, uint64_t asn)
+    void
+    demapDataPage(Addr vaddr, uint64_t asn)
     {
         this->dtb->demapPage(vaddr, asn);
     }
@@ -491,12 +507,12 @@ class CheckerCPU : public BaseCPU, public ExecContext
     Fault writeMem(uint8_t *data, unsigned size, Addr addr,
                    Request::Flags flags, uint64_t *res) override;
 
-    unsigned int readStCondFailures() const override {
+    unsigned int
+    readStCondFailures() const override {
         return thread->readStCondFailures();
     }
 
-    void setStCondFailures(unsigned int sc_failures) override
-    {}
+    void setStCondFailures(unsigned int sc_failures) override {}
     /////////////////////////////////////////////////////
 
     Fault hwrei() override { return thread->hwrei(); }
@@ -507,7 +523,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
     // The checker's state would have already been updated by the syscall.
     void syscall(int64_t callnum, Fault *fault) override { }
 
-    void handleError()
+    void
+    handleError()
     {
         if (exitOnError)
             dumpAndExit();
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 85053dfa6..854771fdd 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -206,11 +206,13 @@ class CheckerThreadContext : public ThreadContext
     //
     // New accessors for new decoder.
     //
-    uint64_t readIntReg(int reg_idx)
-    { return actualTC->readIntReg(reg_idx); }
+    RegVal readIntReg(int reg_idx) { return actualTC->readIntReg(reg_idx); }
 
-    FloatRegBits readFloatRegBits(int reg_idx)
-    { return actualTC->readFloatRegBits(reg_idx); }
+    RegVal
+    readFloatRegBits(int reg_idx)
+    {
+        return actualTC->readFloatRegBits(reg_idx);
+    }
 
     const VecRegContainer& readVecReg(const RegId& reg) const
     { return actualTC->readVecReg(reg); }
@@ -264,31 +266,36 @@ class CheckerThreadContext : public ThreadContext
     CCReg readCCReg(int reg_idx)
     { return actualTC->readCCReg(reg_idx); }
 
-    void setIntReg(int reg_idx, uint64_t val)
+    void
+    setIntReg(int reg_idx, RegVal val)
     {
         actualTC->setIntReg(reg_idx, val);
         checkerTC->setIntReg(reg_idx, val);
     }
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val)
+    void
+    setFloatRegBits(int reg_idx, RegVal val)
     {
         actualTC->setFloatRegBits(reg_idx, val);
         checkerTC->setFloatRegBits(reg_idx, val);
     }
 
-    void setVecReg(const RegId& reg, const VecRegContainer& val)
+    void
+    setVecReg(const RegId& reg, const VecRegContainer& val)
     {
         actualTC->setVecReg(reg, val);
         checkerTC->setVecReg(reg, val);
     }
 
-    void setVecElem(const RegId& reg, const VecElem& val)
+    void
+    setVecElem(const RegId& reg, const VecElem& val)
     {
         actualTC->setVecElem(reg, val);
         checkerTC->setVecElem(reg, val);
     }
 
-    void setCCReg(int reg_idx, CCReg val)
+    void
+    setCCReg(int reg_idx, CCReg val)
     {
         actualTC->setCCReg(reg_idx, val);
         checkerTC->setCCReg(reg_idx, val);
@@ -299,7 +306,8 @@ class CheckerThreadContext : public ThreadContext
     { return actualTC->pcState(); }
 
     /** Sets this thread's PC state. */
-    void pcState(const TheISA::PCState &val)
+    void
+    pcState(const TheISA::PCState &val)
     {
         DPRINTF(Checker, "Changing PC to %s, old PC %s\n",
                          val, checkerTC->pcState());
@@ -308,13 +316,15 @@ class CheckerThreadContext : public ThreadContext
         return actualTC->pcState(val);
     }
 
-    void setNPC(Addr val)
+    void
+    setNPC(Addr val)
     {
         checkerTC->setNPC(val);
         actualTC->setNPC(val);
     }
 
-    void pcStateNoRecord(const TheISA::PCState &val)
+    void
+    pcStateNoRecord(const TheISA::PCState &val)
     {
         return actualTC->pcState(val);
     }
@@ -331,13 +341,14 @@ class CheckerThreadContext : public ThreadContext
     MicroPC microPC()
     { return actualTC->microPC(); }
 
-    MiscReg readMiscRegNoEffect(int misc_reg) const
+    RegVal readMiscRegNoEffect(int misc_reg) const
     { return actualTC->readMiscRegNoEffect(misc_reg); }
 
-    MiscReg readMiscReg(int misc_reg)
+    RegVal readMiscReg(int misc_reg)
     { return actualTC->readMiscReg(misc_reg); }
 
-    void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+    void
+    setMiscRegNoEffect(int misc_reg, const RegVal &val)
     {
         DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
                          " and O3..\n", misc_reg);
@@ -345,7 +356,8 @@ class CheckerThreadContext : public ThreadContext
         actualTC->setMiscRegNoEffect(misc_reg, val);
     }
 
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void
+    setMiscReg(int misc_reg, const RegVal &val)
     {
         DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
                          " and O3..\n", misc_reg);
@@ -353,40 +365,57 @@ class CheckerThreadContext : public ThreadContext
         actualTC->setMiscReg(misc_reg, val);
     }
 
-    RegId flattenRegId(const RegId& regId) const {
+    RegId
+    flattenRegId(const RegId& regId) const
+    {
         return actualTC->flattenRegId(regId);
     }
 
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }
 
-    void setStCondFailures(unsigned sc_failures)
+    void
+    setStCondFailures(unsigned sc_failures)
     {
         actualTC->setStCondFailures(sc_failures);
     }
 
     Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
 
-    uint64_t readIntRegFlat(int idx)
-    { return actualTC->readIntRegFlat(idx); }
+    RegVal readIntRegFlat(int idx) { return actualTC->readIntRegFlat(idx); }
 
-    void setIntRegFlat(int idx, uint64_t val)
-    { actualTC->setIntRegFlat(idx, val); }
+    void
+    setIntRegFlat(int idx, RegVal val)
+    {
+        actualTC->setIntRegFlat(idx, val);
+    }
 
-    FloatRegBits readFloatRegBitsFlat(int idx)
-    { return actualTC->readFloatRegBitsFlat(idx); }
+    RegVal
+    readFloatRegBitsFlat(int idx)
+    {
+        return actualTC->readFloatRegBitsFlat(idx);
+    }
 
-    void setFloatRegBitsFlat(int idx, FloatRegBits val)
-    { actualTC->setFloatRegBitsFlat(idx, val); }
+    void
+    setFloatRegBitsFlat(int idx, RegVal val)
+    {
+        actualTC->setFloatRegBitsFlat(idx, val);
+    }
 
-    const VecRegContainer& readVecRegFlat(int idx) const
-    { return actualTC->readVecRegFlat(idx); }
+    const VecRegContainer &
+    readVecRegFlat(int idx) const
+    {
+        return actualTC->readVecRegFlat(idx);
+    }
 
     /**
      * Read vector register for modification, flat indexing.
      */
-    VecRegContainer& getWritableVecRegFlat(int idx)
-    { return actualTC->getWritableVecRegFlat(idx); }
+    VecRegContainer &
+    getWritableVecRegFlat(int idx)
+    {
+        return actualTC->getWritableVecRegFlat(idx);
+    }
 
     void setVecRegFlat(int idx, const VecRegContainer& val)
     { actualTC->setVecRegFlat(idx, val); }