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authorKevin Lim <ktlim@umich.edu>2006-06-06 17:32:21 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-06 17:32:21 -0400
commiteb0e416998ce2546c768d2b9d9d8bf3a387a87be (patch)
tree14064a3b184dbc36e9c0576c120ab209734fe45d /src/cpu/cpu_exec_context.cc
parent0f014e4340bb0991716cb0f0feafd48b53e865d7 (diff)
downloadgem5-eb0e416998ce2546c768d2b9d9d8bf3a387a87be.tar.xz
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar. src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext. --HG-- rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
Diffstat (limited to 'src/cpu/cpu_exec_context.cc')
-rw-r--r--src/cpu/cpu_exec_context.cc60
1 files changed, 30 insertions, 30 deletions
diff --git a/src/cpu/cpu_exec_context.cc b/src/cpu/cpu_exec_context.cc
index 1227d52f5..1e8071ca8 100644
--- a/src/cpu/cpu_exec_context.cc
+++ b/src/cpu/cpu_exec_context.cc
@@ -36,7 +36,7 @@
#include "arch/isa_traits.hh"
#include "cpu/base.hh"
#include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#if FULL_SYSTEM
#include "base/callback.hh"
@@ -62,14 +62,14 @@ using namespace std;
CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
AlphaITB *_itb, AlphaDTB *_dtb,
bool use_kernel_stats)
- : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
+ : _status(ThreadContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb),
dtb(_dtb), profile(NULL), func_exe_inst(0), storeCondFailures(0)
{
- proxy = new ProxyExecContext<CPUExecContext>(this);
+ tc = new ProxyThreadContext<CPUExecContext>(this);
- quiesceEvent = new EndQuiesceEvent(proxy);
+ quiesceEvent = new EndQuiesceEvent(tc);
regs.clear();
@@ -109,7 +109,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
#else
CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
Process *_process, int _asid, MemObject* memobj)
- : _status(ExecContext::Unallocated),
+ : _status(ThreadContext::Unallocated),
cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0),
lastSuspend(0), process(_process), asid(_asid),
func_exe_inst(0), storeCondFailures(0)
@@ -124,7 +124,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
port->setPeer(mem_port);
regs.clear();
- proxy = new ProxyExecContext<CPUExecContext>(this);
+ tc = new ProxyThreadContext<CPUExecContext>(this);
}
CPUExecContext::CPUExecContext(RegFile *regFile)
@@ -132,14 +132,14 @@ CPUExecContext::CPUExecContext(RegFile *regFile)
func_exe_inst(0), storeCondFailures(0)
{
regs = *regFile;
- proxy = new ProxyExecContext<CPUExecContext>(this);
+ tc = new ProxyThreadContext<CPUExecContext>(this);
}
#endif
CPUExecContext::~CPUExecContext()
{
- delete proxy;
+ delete tc;
}
#if FULL_SYSTEM
@@ -147,7 +147,7 @@ void
CPUExecContext::dumpFuncProfile()
{
std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
- profile->dump(proxy, *os);
+ profile->dump(tc, *os);
}
void
@@ -167,7 +167,7 @@ CPUExecContext::profileSample()
#endif
void
-CPUExecContext::takeOverFrom(ExecContext *oldContext)
+CPUExecContext::takeOverFrom(ThreadContext *oldContext)
{
// some things should already be set up
#if FULL_SYSTEM
@@ -185,18 +185,18 @@ CPUExecContext::takeOverFrom(ExecContext *oldContext)
#else
EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
if (quiesce) {
- // Point the quiesce event's XC at this XC so that it wakes up
+ // Point the quiesce event's TC at this TC so that it wakes up
// the proper CPU.
- quiesce->xc = proxy;
+ quiesce->tc = tc;
}
if (quiesceEvent) {
- quiesceEvent->xc = proxy;
+ quiesceEvent->tc = tc;
}
#endif
storeCondFailures = 0;
- oldContext->setStatus(ExecContext::Unallocated);
+ oldContext->setStatus(ThreadContext::Unallocated);
}
void
@@ -242,17 +242,17 @@ CPUExecContext::unserialize(Checkpoint *cp, const std::string &section)
void
CPUExecContext::activate(int delay)
{
- if (status() == ExecContext::Active)
+ if (status() == ThreadContext::Active)
return;
lastActivate = curTick;
- if (status() == ExecContext::Unallocated) {
+ if (status() == ThreadContext::Unallocated) {
cpu->activateWhenReady(thread_num);
return;
}
- _status = ExecContext::Active;
+ _status = ThreadContext::Active;
// status() == Suspended
cpu->activateContext(thread_num, delay);
@@ -261,7 +261,7 @@ CPUExecContext::activate(int delay)
void
CPUExecContext::suspend()
{
- if (status() == ExecContext::Suspended)
+ if (status() == ThreadContext::Suspended)
return;
lastActivate = curTick;
@@ -270,32 +270,32 @@ CPUExecContext::suspend()
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
if (cpu->check_interrupts()) {
- assert(status() == ExecContext::Active);
+ assert(status() == ThreadContext::Active);
return;
}
#endif
*/
- _status = ExecContext::Suspended;
+ _status = ThreadContext::Suspended;
cpu->suspendContext(thread_num);
}
void
CPUExecContext::deallocate()
{
- if (status() == ExecContext::Unallocated)
+ if (status() == ThreadContext::Unallocated)
return;
- _status = ExecContext::Unallocated;
+ _status = ThreadContext::Unallocated;
cpu->deallocateContext(thread_num);
}
void
CPUExecContext::halt()
{
- if (status() == ExecContext::Halted)
+ if (status() == ThreadContext::Halted)
return;
- _status = ExecContext::Halted;
+ _status = ThreadContext::Halted;
cpu->haltContext(thread_num);
}
@@ -310,22 +310,22 @@ CPUExecContext::regStats(const string &name)
}
void
-CPUExecContext::copyArchRegs(ExecContext *xc)
+CPUExecContext::copyArchRegs(ThreadContext *src_tc)
{
- TheISA::copyRegs(xc, proxy);
+ TheISA::copyRegs(src_tc, tc);
}
#if FULL_SYSTEM
VirtualPort*
-CPUExecContext::getVirtPort(ExecContext *xc)
+CPUExecContext::getVirtPort(ThreadContext *src_tc)
{
- if (!xc)
+ if (!src_tc)
return virtPort;
VirtualPort *vp;
Port *mem_port;
- vp = new VirtualPort("xc-vport", xc);
+ vp = new VirtualPort("tc-vport", src_tc);
mem_port = system->physmem->getPort("functional");
mem_port->setPeer(vp);
vp->setPeer(mem_port);
@@ -335,7 +335,7 @@ CPUExecContext::getVirtPort(ExecContext *xc)
void
CPUExecContext::delVirtPort(VirtualPort *vp)
{
-// assert(!vp->nullExecContext());
+// assert(!vp->nullThreadContext());
delete vp->getPeer();
delete vp;
}