Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.

src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
    Change ExecContext to ThreadContext.

--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e

1 files changed, 14 insertions, 14 deletions

diff --git a/src/cpu/cpu_exec_context.hh b/src/cpu/cpu_exec_context.hh
index 5faa8d19c..01b5cbb15 100644
--- a/src/cpu/cpu_exec_context.hh
+++ b/src/cpu/cpu_exec_context.hh
@@ -34,7 +34,7 @@
 
 #include "arch/isa_traits.hh"
 #include "config/full_system.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "mem/physical.hh"
 #include "mem/request.hh"
 #include "sim/byteswap.hh"
@@ -84,7 +84,7 @@ class CPUExecContext
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
   public:
-    typedef ExecContext::Status Status;
+    typedef ThreadContext::Status Status;
 
   private:
     Status _status;
@@ -114,7 +114,7 @@ class CPUExecContext
     // pointer to CPU associated with this context
     BaseCPU *cpu;
 
-    ProxyExecContext<CPUExecContext> *proxy;
+    ProxyThreadContext<CPUExecContext> *tc;
 
     // Current instruction
     MachInst inst;
@@ -215,7 +215,7 @@ class CPUExecContext
 #endif
     virtual ~CPUExecContext();
 
-    virtual void takeOverFrom(ExecContext *oldContext);
+    virtual void takeOverFrom(ThreadContext *oldContext);
 
     void regStats(const std::string &name);
 
@@ -224,7 +224,7 @@ class CPUExecContext
 
     BaseCPU *getCpuPtr() { return cpu; }
 
-    ExecContext *getProxy() { return proxy; }
+    ThreadContext *getTC() { return tc; }
 
     int getThreadNum() { return thread_num; }
 
@@ -240,25 +240,25 @@ class CPUExecContext
 
     Fault translateInstReq(RequestPtr &req)
     {
-        return itb->translate(req, proxy);
+        return itb->translate(req, tc);
     }
 
     Fault translateDataReadReq(RequestPtr &req)
     {
-        return dtb->translate(req, proxy, false);
+        return dtb->translate(req, tc, false);
     }
 
     Fault translateDataWriteReq(RequestPtr &req)
     {
-        return dtb->translate(req, proxy, true);
+        return dtb->translate(req, tc, true);
     }
 
     FunctionalPort *getPhysPort() { return physPort; }
 
-    /** Return a virtual port. If no exec context is specified then a static
+    /** Return a virtual port. If no thread context is specified then a static
      * port is returned. Otherwise a port is created and returned. It must be
      * deleted by deleteVirtPort(). */
-    VirtualPort *getVirtPort(ExecContext *xc);
+    VirtualPort *getVirtPort(ThreadContext *tc);
 
     void delVirtPort(VirtualPort *vp);
 
@@ -377,7 +377,7 @@ class CPUExecContext
 
     int readCpuId() { return cpu_id; }
 
-    void copyArchRegs(ExecContext *xc);
+    void copyArchRegs(ThreadContext *tc);
 
     //
     // New accessors for new decoder.
@@ -470,7 +470,7 @@ class CPUExecContext
 
     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
     {
-        return regs.readMiscRegWithEffect(misc_reg, fault, proxy);
+        return regs.readMiscRegWithEffect(misc_reg, fault, tc);
     }
 
     Fault setMiscReg(int misc_reg, const MiscReg &val)
@@ -480,7 +480,7 @@ class CPUExecContext
 
     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
-        return regs.setMiscRegWithEffect(misc_reg, val, proxy);
+        return regs.setMiscRegWithEffect(misc_reg, val, tc);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }
@@ -517,7 +517,7 @@ class CPUExecContext
 
     void syscall(int64_t callnum)
     {
-        process->syscall(callnum, proxy);
+        process->syscall(callnum, tc);
     }
 
     Counter readFuncExeInst() { return func_exe_inst; }