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author | Korey Sewell <ksewell@umich.edu> | 2006-06-30 20:51:07 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2006-06-30 20:51:07 -0400 |
commit | ed821702e02b9c02c3b5f18dc61dad1f0fbc7164 (patch) | |
tree | e299605370852ed8331e512b92590f0fcd875f9d /src/cpu/cpu_models.py | |
parent | 7a4929813423c6f72827c58453cb9bd591f1801c (diff) | |
parent | 51261196bde3403544631cdb4895c2d2a51c3f1e (diff) | |
download | gem5-ed821702e02b9c02c3b5f18dc61dad1f0fbc7164.tar.xz |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : 3c1405d8b4831c6240e02ba65a72043ca55f4a46
Diffstat (limited to 'src/cpu/cpu_models.py')
-rw-r--r-- | src/cpu/cpu_models.py | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/src/cpu/cpu_models.py b/src/cpu/cpu_models.py index e7ef9ab42..1add32745 100644 --- a/src/cpu/cpu_models.py +++ b/src/cpu/cpu_models.py @@ -26,6 +26,10 @@ # # Authors: Steve Reinhardt +import os +import os.path +import sys + ################ # CpuModel class # @@ -47,7 +51,6 @@ class CpuModel: # Add self to dict CpuModel.dict[name] = self - # # Define CPU models. # @@ -67,9 +70,6 @@ CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc', CpuModel('FullCPU', 'full_cpu_exec.cc', '#include "encumbered/cpu/full/dyn_inst.hh"', { 'CPU_exec_context': 'DynInst' }) -CpuModel('AlphaO3CPU', 'alpha_o3_exec.cc', - '#include "cpu/o3/alpha_dyn_inst.hh"', - { 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' }) CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc', '#include "cpu/ozone/dyn_inst.hh"', { 'CPU_exec_context': 'OzoneDynInst<SimpleImpl>' }) @@ -80,3 +80,17 @@ CpuModel('CheckerCPU', 'checker_cpu_exec.cc', '#include "cpu/checker/cpu.hh"', { 'CPU_exec_context': 'CheckerCPU' }) +# Maybe there is a more clever way to determine ISA +# here but since the environment variable isnt passed through +# here the easiest way is this... +sub_template = 'not found' +for argument in sys.argv: + if 'ALPHA' in argument: + sub_template = 'AlphaDynInst<AlphaSimpleImpl>' + +if sub_template == 'not found': + sys.exit('NO CPU_exec_context substitution defined for this ISA') + +CpuModel('O3CPU', 'o3_cpu_exec.cc', + '#include "cpu/o3/isa_specific.hh"', + { 'CPU_exec_context': sub_template }) |