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author | Gabe Black <gblack@eecs.umich.edu> | 2011-09-09 02:30:01 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2011-09-09 02:30:01 -0700 |
commit | b7b545bc38bcd9ee54f1b8e45064cd8b7a3070b0 (patch) | |
tree | e81962e78194fa13c768e6a841f367bd71dd5c83 /src/cpu/decode_cache.hh | |
parent | c5fd6f4fec147dbdbbd46794bdbbf5782ea7a57d (diff) | |
download | gem5-b7b545bc38bcd9ee54f1b8e45064cd8b7a3070b0.tar.xz |
Decode: Pull instruction decoding out of the StaticInst class into its own.
This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.
Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.
Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
Diffstat (limited to 'src/cpu/decode_cache.hh')
-rw-r--r-- | src/cpu/decode_cache.hh | 179 |
1 files changed, 179 insertions, 0 deletions
diff --git a/src/cpu/decode_cache.hh b/src/cpu/decode_cache.hh new file mode 100644 index 000000000..1bff315d1 --- /dev/null +++ b/src/cpu/decode_cache.hh @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2011 Google + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __CPU_DECODE_CACHE_HH__ +#define __CPU_DECODE_CACHE_HH__ + +#include "arch/isa_traits.hh" +#include "arch/types.hh" +#include "base/hashmap.hh" +#include "config/the_isa.hh" +#include "cpu/static_inst.hh" + +typedef StaticInstPtr (*DecodeInstFunc)(TheISA::ExtMachInst); + +template <DecodeInstFunc decodeInstFunc> +class DecodeCache +{ + private: + typedef TheISA::ExtMachInst ExtMachInst; + + /// Hash of decoded instructions. + typedef m5::hash_map<ExtMachInst, StaticInstPtr> InstMap; + InstMap instMap; + + /// A table of instructions which are already been decoded, indexed by + /// page offset. + class DecodePage + { + protected: + StaticInstPtr instructions[TheISA::PageBytes]; + + // A helper function to compute the index of an address in the table. + Addr offset(Addr addr) { return addr & (TheISA::PageBytes - 1); } + + public: + /// Decode the given instruction. First attempt to find it in the + /// table, then in the generic decode cache, and finally call the + /// actual decode function. + /// + /// @param mach_inst The predecoded instruction to decode. + /// @param addr The address the instruction came from. + /// @param cache A cache of already decoded instructions. + /// @retval The decoded instruction object. + StaticInstPtr + decode(const ExtMachInst &mach_inst, Addr addr, InstMap &instMap) + { + StaticInstPtr si = instructions[offset(addr)]; + if (si && (si->machInst == mach_inst)) { + return si; + } + + InstMap::iterator iter = instMap.find(mach_inst); + if (iter != instMap.end()) { + si = iter->second; + } else { + si = decodeInstFunc(mach_inst); + instMap[mach_inst] = si; + } + + instructions[offset(addr)] = si; + return si; + } + }; + + /// A store of DecodePages. Basically a slightly smarter hash_map. + class DecodePages + { + protected: + typedef typename m5::hash_map<Addr, DecodePage *> PageMap; + typedef typename PageMap::iterator PageIt; + PageIt recent[2]; + PageMap pageMap; + + /// Update the small cache of recent lookups. + /// @param recentest The most recent result; + void + update(PageIt recentest) + { + recent[1] = recent[0]; + recent[0] = recentest; + } + + public: + /// Constructor + DecodePages() + { + recent[0] = recent[1] = pageMap.end(); + } + + /// Attempt to find the DecodePage which goes with a particular + /// address. First check the small cache of recent results, then + /// actually look in the hash_map. + /// @param addr The address to look up. + DecodePage * + findPage(Addr addr) + { + Addr page_addr = addr & ~(TheISA::PageBytes - 1); + + // Check against recent lookups. + if (recent[0] != pageMap.end()) { + if (recent[0]->first == page_addr) + return recent[0]->second; + if (recent[1] != pageMap.end() && + recent[1]->first == page_addr) { + update(recent[1]); + // recent[1] has just become recent[0]. + return recent[0]->second; + } + } + + // Actually look in the has_map. + PageIt it = pageMap.find(page_addr); + if (it != pageMap.end()) { + update(it); + return it->second; + } + + // Didn't find it so return NULL. + return NULL; + } + + void + addPage(Addr addr, DecodePage *page) + { + Addr page_addr = addr & ~(TheISA::PageBytes - 1); + typename PageMap::value_type to_insert(page_addr, page); + update(pageMap.insert(to_insert).first); + } + } decodePages; + + public: + /// Decode a machine instruction. + /// @param mach_inst The binary instruction to decode. + /// @retval A pointer to the corresponding StaticInst object. + StaticInstPtr + decode(ExtMachInst mach_inst, Addr addr) + { + // Try to find a matching address based table of instructions. + DecodePage *page = decodePages.findPage(addr); + if (!page) { + // Nothing was found, so create a new one. + page = new DecodePage; + decodePages.addPage(addr, page); + } + + // Use the table to decode the instruction. It will fall back to other + // mechanisms if it needs to. + return page->decode(mach_inst, addr, instMap); + } +}; + +#endif // __CPU_DECODE_CACHE_HH__ |