diff options
| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/cpu/exec_context.hh | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/cpu/exec_context.hh')
| -rw-r--r-- | src/cpu/exec_context.hh | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index b21f0767a..1b6084e27 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -49,6 +49,7 @@ #include "base/types.hh" #include "config/the_isa.hh" #include "cpu/base.hh" +#include "cpu/reg_class.hh" #include "cpu/static_inst_fwd.hh" #include "cpu/translation.hh" #include "mem/request.hh" @@ -286,9 +287,9 @@ class ExecContext { */ #if THE_ISA == MIPS_ISA - virtual MiscReg readRegOtherThread(int regIdx, + virtual MiscReg readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID) = 0; - virtual void setRegOtherThread(int regIdx, MiscReg val, + virtual void setRegOtherThread(RegId reg, MiscReg val, ThreadID tid = InvalidThreadID) = 0; #endif |