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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-01 16:44:45 -0500 |
| commit | 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 (patch) | |
| tree | 736bc7ea34184fb103fd836e67672521193602a7 /src/cpu/exec_context.hh | |
| parent | f3ba6d20f6070c30418866e627e2418f39b433dd (diff) | |
| download | gem5-2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0.tar.xz | |
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
Diffstat (limited to 'src/cpu/exec_context.hh')
| -rw-r--r-- | src/cpu/exec_context.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index e28b33193..13f70fa79 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -101,14 +101,14 @@ class ExecContext { /** Reads a miscellaneous register, handling any architectural * side effects due to reading that register. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault); + MiscReg readMiscRegWithEffect(int misc_reg); /** Sets a miscellaneous register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val); + void setMiscReg(int misc_reg, const MiscReg &val); /** Sets a miscellaneous register, handling any architectural * side effects due to writing that register. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); + void setMiscRegWithEffect(int misc_reg, const MiscReg &val); /** Records the effective address of the instruction. Only valid * for memory ops. */ |