Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.

src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
    Change ExecContext to ThreadContext.

--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e

1 files changed, 0 insertions, 419 deletions

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
deleted file mode 100644
index c9a060b0b..000000000
--- a/src/cpu/exec_context.hh
+++ /dev/null
@@ -1,419 +0,0 @@
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_EXEC_CONTEXT_HH__
-#define __CPU_EXEC_CONTEXT_HH__
-
-#include "config/full_system.hh"
-#include "mem/request.hh"
-#include "sim/faults.hh"
-#include "sim/host.hh"
-#include "sim/serialize.hh"
-#include "sim/byteswap.hh"
-
-// @todo: Figure out a more architecture independent way to obtain the ITB and
-// DTB pointers.
-class AlphaDTB;
-class AlphaITB;
-class BaseCPU;
-class EndQuiesceEvent;
-class Event;
-class TranslatingPort;
-class FunctionalPort;
-class VirtualPort;
-class Process;
-class System;
-namespace Kernel {
-    class Statistics;
-};
-
-class ExecContext
-{
-  protected:
-    typedef TheISA::RegFile RegFile;
-    typedef TheISA::MachInst MachInst;
-    typedef TheISA::IntReg IntReg;
-    typedef TheISA::FloatReg FloatReg;
-    typedef TheISA::FloatRegBits FloatRegBits;
-    typedef TheISA::MiscRegFile MiscRegFile;
-    typedef TheISA::MiscReg MiscReg;
-  public:
-    enum Status
-    {
-        /// Initialized but not running yet.  All CPUs start in
-        /// this state, but most transition to Active on cycle 1.
-        /// In MP or SMT systems, non-primary contexts will stay
-        /// in this state until a thread is assigned to them.
-        Unallocated,
-
-        /// Running.  Instructions should be executed only when
-        /// the context is in this state.
-        Active,
-
-        /// Temporarily inactive.  Entered while waiting for
-        /// synchronization, etc.
-        Suspended,
-
-        /// Permanently shut down.  Entered when target executes
-        /// m5exit pseudo-instruction.  When all contexts enter
-        /// this state, the simulation will terminate.
-        Halted
-    };
-
-    virtual ~ExecContext() { };
-
-    virtual BaseCPU *getCpuPtr() = 0;
-
-    virtual void setCpuId(int id) = 0;
-
-    virtual int readCpuId() = 0;
-
-#if FULL_SYSTEM
-    virtual System *getSystemPtr() = 0;
-
-    virtual AlphaITB *getITBPtr() = 0;
-
-    virtual AlphaDTB * getDTBPtr() = 0;
-
-    virtual Kernel::Statistics *getKernelStats() = 0;
-
-    virtual FunctionalPort *getPhysPort() = 0;
-
-    virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0;
-
-    virtual void delVirtPort(VirtualPort *vp) = 0;
-#else
-    virtual TranslatingPort *getMemPort() = 0;
-
-    virtual Process *getProcessPtr() = 0;
-#endif
-
-    virtual Status status() const = 0;
-
-    virtual void setStatus(Status new_status) = 0;
-
-    /// Set the status to Active.  Optional delay indicates number of
-    /// cycles to wait before beginning execution.
-    virtual void activate(int delay = 1) = 0;
-
-    /// Set the status to Suspended.
-    virtual void suspend() = 0;
-
-    /// Set the status to Unallocated.
-    virtual void deallocate() = 0;
-
-    /// Set the status to Halted.
-    virtual void halt() = 0;
-
-#if FULL_SYSTEM
-    virtual void dumpFuncProfile() = 0;
-#endif
-
-    virtual void takeOverFrom(ExecContext *old_context) = 0;
-
-    virtual void regStats(const std::string &name) = 0;
-
-    virtual void serialize(std::ostream &os) = 0;
-    virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
-
-#if FULL_SYSTEM
-    virtual EndQuiesceEvent *getQuiesceEvent() = 0;
-
-    // Not necessarily the best location for these...
-    // Having an extra function just to read these is obnoxious
-    virtual Tick readLastActivate() = 0;
-    virtual Tick readLastSuspend() = 0;
-
-    virtual void profileClear() = 0;
-    virtual void profileSample() = 0;
-#endif
-
-    virtual int getThreadNum() = 0;
-
-    // Also somewhat obnoxious.  Really only used for the TLB fault.
-    // However, may be quite useful in SPARC.
-    virtual TheISA::MachInst getInst() = 0;
-
-    virtual void copyArchRegs(ExecContext *xc) = 0;
-
-    virtual void clearArchRegs() = 0;
-
-    //
-    // New accessors for new decoder.
-    //
-    virtual uint64_t readIntReg(int reg_idx) = 0;
-
-    virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
-
-    virtual FloatReg readFloatReg(int reg_idx) = 0;
-
-    virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
-
-    virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
-
-    virtual void setIntReg(int reg_idx, uint64_t val) = 0;
-
-    virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
-
-    virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
-
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
-
-    virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
-
-    virtual uint64_t readPC() = 0;
-
-    virtual void setPC(uint64_t val) = 0;
-
-    virtual uint64_t readNextPC() = 0;
-
-    virtual void setNextPC(uint64_t val) = 0;
-
-    virtual uint64_t readNextNPC() = 0;
-
-    virtual void setNextNPC(uint64_t val) = 0;
-
-    virtual MiscReg readMiscReg(int misc_reg) = 0;
-
-    virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
-
-    virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
-
-    virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
-
-    // Also not necessarily the best location for these two.  Hopefully will go
-    // away once we decide upon where st cond failures goes.
-    virtual unsigned readStCondFailures() = 0;
-
-    virtual void setStCondFailures(unsigned sc_failures) = 0;
-
-#if FULL_SYSTEM
-    virtual bool inPalMode() = 0;
-#endif
-
-    // Only really makes sense for old CPU model.  Still could be useful though.
-    virtual bool misspeculating() = 0;
-
-#if !FULL_SYSTEM
-    virtual IntReg getSyscallArg(int i) = 0;
-
-    // used to shift args for indirect syscall
-    virtual void setSyscallArg(int i, IntReg val) = 0;
-
-    virtual void setSyscallReturn(SyscallReturn return_value) = 0;
-
-
-    // Same with st cond failures.
-    virtual Counter readFuncExeInst() = 0;
-#endif
-
-    virtual void changeRegFileContext(RegFile::ContextParam param,
-            RegFile::ContextVal val) = 0;
-};
-
-template <class XC>
-class ProxyExecContext : public ExecContext
-{
-  public:
-    ProxyExecContext(XC *actual_xc)
-    { actualXC = actual_xc; }
-
-  private:
-    XC *actualXC;
-
-  public:
-
-    BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
-
-    void setCpuId(int id) { actualXC->setCpuId(id); }
-
-    int readCpuId() { return actualXC->readCpuId(); }
-
-#if FULL_SYSTEM
-    System *getSystemPtr() { return actualXC->getSystemPtr(); }
-
-    AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
-
-    AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
-
-    Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); }
-
-    FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); }
-
-    VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); }
-
-    void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); }
-#else
-    TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
-
-    Process *getProcessPtr() { return actualXC->getProcessPtr(); }
-#endif
-
-    Status status() const { return actualXC->status(); }
-
-    void setStatus(Status new_status) { actualXC->setStatus(new_status); }
-
-    /// Set the status to Active.  Optional delay indicates number of
-    /// cycles to wait before beginning execution.
-    void activate(int delay = 1) { actualXC->activate(delay); }
-
-    /// Set the status to Suspended.
-    void suspend() { actualXC->suspend(); }
-
-    /// Set the status to Unallocated.
-    void deallocate() { actualXC->deallocate(); }
-
-    /// Set the status to Halted.
-    void halt() { actualXC->halt(); }
-
-#if FULL_SYSTEM
-    void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
-#endif
-
-    void takeOverFrom(ExecContext *oldContext)
-    { actualXC->takeOverFrom(oldContext); }
-
-    void regStats(const std::string &name) { actualXC->regStats(name); }
-
-    void serialize(std::ostream &os) { actualXC->serialize(os); }
-    void unserialize(Checkpoint *cp, const std::string &section)
-    { actualXC->unserialize(cp, section); }
-
-#if FULL_SYSTEM
-    EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
-
-    Tick readLastActivate() { return actualXC->readLastActivate(); }
-    Tick readLastSuspend() { return actualXC->readLastSuspend(); }
-
-    void profileClear() { return actualXC->profileClear(); }
-    void profileSample() { return actualXC->profileSample(); }
-#endif
-
-    int getThreadNum() { return actualXC->getThreadNum(); }
-
-    // @todo: Do I need this?
-    MachInst getInst() { return actualXC->getInst(); }
-
-    // @todo: Do I need this?
-    void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); }
-
-    void clearArchRegs() { actualXC->clearArchRegs(); }
-
-    //
-    // New accessors for new decoder.
-    //
-    uint64_t readIntReg(int reg_idx)
-    { return actualXC->readIntReg(reg_idx); }
-
-    FloatReg readFloatReg(int reg_idx, int width)
-    { return actualXC->readFloatReg(reg_idx, width); }
-
-    FloatReg readFloatReg(int reg_idx)
-    { return actualXC->readFloatReg(reg_idx); }
-
-    FloatRegBits readFloatRegBits(int reg_idx, int width)
-    { return actualXC->readFloatRegBits(reg_idx, width); }
-
-    FloatRegBits readFloatRegBits(int reg_idx)
-    { return actualXC->readFloatRegBits(reg_idx); }
-
-    void setIntReg(int reg_idx, uint64_t val)
-    { actualXC->setIntReg(reg_idx, val); }
-
-    void setFloatReg(int reg_idx, FloatReg val, int width)
-    { actualXC->setFloatReg(reg_idx, val, width); }
-
-    void setFloatReg(int reg_idx, FloatReg val)
-    { actualXC->setFloatReg(reg_idx, val); }
-
-    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
-    { actualXC->setFloatRegBits(reg_idx, val, width); }
-
-    void setFloatRegBits(int reg_idx, FloatRegBits val)
-    { actualXC->setFloatRegBits(reg_idx, val); }
-
-    uint64_t readPC() { return actualXC->readPC(); }
-
-    void setPC(uint64_t val) { actualXC->setPC(val); }
-
-    uint64_t readNextPC() { return actualXC->readNextPC(); }
-
-    void setNextPC(uint64_t val) { actualXC->setNextPC(val); }
-
-    uint64_t readNextNPC() { return actualXC->readNextNPC(); }
-
-    void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); }
-
-    MiscReg readMiscReg(int misc_reg)
-    { return actualXC->readMiscReg(misc_reg); }
-
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
-    { return actualXC->readMiscRegWithEffect(misc_reg, fault); }
-
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
-    { return actualXC->setMiscReg(misc_reg, val); }
-
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
-    { return actualXC->setMiscRegWithEffect(misc_reg, val); }
-
-    unsigned readStCondFailures()
-    { return actualXC->readStCondFailures(); }
-
-    void setStCondFailures(unsigned sc_failures)
-    { actualXC->setStCondFailures(sc_failures); }
-#if FULL_SYSTEM
-    bool inPalMode() { return actualXC->inPalMode(); }
-#endif
-
-    // @todo: Fix this!
-    bool misspeculating() { return actualXC->misspeculating(); }
-
-#if !FULL_SYSTEM
-    IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
-
-    // used to shift args for indirect syscall
-    void setSyscallArg(int i, IntReg val)
-    { actualXC->setSyscallArg(i, val); }
-
-    void setSyscallReturn(SyscallReturn return_value)
-    { actualXC->setSyscallReturn(return_value); }
-
-
-    Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
-#endif
-
-    void changeRegFileContext(RegFile::ContextParam param,
-            RegFile::ContextVal val)
-    {
-        actualXC->changeRegFileContext(param, val);
-    }
-};
-
-#endif