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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-28 01:58:04 -0500 |
commit | aafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch) | |
tree | d40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/cpu/exec_context.hh | |
parent | 608641e23c7f2288810c3f23a1a63790b664f2ab (diff) | |
download | gem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz |
revert 5af8f40d8f2c
Diffstat (limited to 'src/cpu/exec_context.hh')
-rw-r--r-- | src/cpu/exec_context.hh | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index 5c6b3fad7..c65841db2 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -76,7 +76,6 @@ class ExecContext { typedef TheISA::MiscReg MiscReg; typedef TheISA::CCReg CCReg; - typedef TheISA::VectorReg VectorReg; public: /** @@ -129,22 +128,6 @@ class ExecContext { /** * @{ - * @name Vector Register Interfaces - * - */ - - /** Reads a vector register. */ - virtual const VectorReg &readVectorRegOperand (const StaticInst *si, - int idx) = 0; - - /** Sets a vector register to a value. */ - virtual void setVectorRegOperand(const StaticInst *si, - int idx, const VectorReg &val) = 0; - - /** @} */ - - /** - * @{ * @name Misc Register Interfaces */ virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; |