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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-30 18:27:04 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-01-30 18:27:04 -0500 |
| commit | ac36fb6e64dadb9eef5c48863b42969a61bbdaec (patch) | |
| tree | 82552f171a4a9239a02b578acd84bca2a9a0a653 /src/cpu/exetrace.cc | |
| parent | fc79ace5023048e5f73e5c1e21b8f86f09f72bf0 (diff) | |
| download | gem5-ac36fb6e64dadb9eef5c48863b42969a61bbdaec.tar.xz | |
add fsr to the list of registers we are interested in
--HG--
extra : convert_revision : 2cc0d0144abab264aa0ec8c07242cdab2dffd4f8
Diffstat (limited to 'src/cpu/exetrace.cc')
| -rw-r--r-- | src/cpu/exetrace.cc | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 85b08ee32..e34ae3731 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -307,6 +307,7 @@ Trace::InstRecord::dump(ostream &outs) bool diffHtba = false; bool diffPstate = false; bool diffY = false; + bool diffFsr = false; bool diffCcr = false; bool diffTl = false; bool diffGl = false; @@ -410,6 +411,8 @@ Trace::InstRecord::dump(ostream &outs) if(shared_data->y != thread->readIntReg(NumIntArchRegs + 1)) diffY = true; + if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) + diffFsr = true; //if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR)) if(shared_data->ccr != thread->readIntReg(NumIntArchRegs + 2)) @@ -450,8 +453,8 @@ Trace::InstRecord::dump(ostream &outs) if ((diffPC || diffCC || diffInst || diffIntRegs || diffFpRegs || diffTpc || diffTnpc || diffTstate || diffTt || diffHpstate || diffHtstate || diffHtba || - diffPstate || diffY || diffCcr || diffTl || diffGl || - diffAsi || diffPil || diffCwp || diffCansave || + diffPstate || diffY || diffCcr || diffTl || diffFsr || + diffGl || diffAsi || diffPil || diffCwp || diffCansave || diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) && !((staticInst->machInst & 0xC1F80000) == 0x81D00000) && !(((staticInst->machInst & 0xC0000000) == 0xC0000000) @@ -487,6 +490,8 @@ Trace::InstRecord::dump(ostream &outs) outs << " [Pstate]"; if (diffY) outs << " [Y]"; + if (diffFsr) + outs << " [FSR]"; if (diffCcr) outs << " [Ccr]"; if (diffTl) @@ -556,6 +561,9 @@ Trace::InstRecord::dump(ostream &outs) //thread->readMiscReg(MISCREG_Y), thread->readIntReg(NumIntArchRegs + 1), shared_data->y); + printRegPair(outs, "FSR", + thread->readMiscReg(MISCREG_FSR), + shared_data->fsr); printRegPair(outs, "Ccr", //thread->readMiscReg(MISCREG_CCR), thread->readIntReg(NumIntArchRegs + 2), |