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| author | Korey Sewell <ksewell@umich.edu> | 2006-07-14 04:52:08 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-07-14 04:52:08 -0400 |
| commit | f1a7e0d3b3dcd04d8bde65ebb7f22b5bc6f98747 (patch) | |
| tree | 179a4ac3d903f991125885643d07f2492cf674bf /src/cpu/exetrace.cc | |
| parent | efc06d0545912f4589e86fe32deac98805786ee6 (diff) | |
| download | gem5-f1a7e0d3b3dcd04d8bde65ebb7f22b5bc6f98747.tar.xz | |
MIPS specific fixes ... the main thing is that SMT threads get their own stack space instead of all stacks start to space
src/arch/mips/isa_traits.hh:
MaxAddr is defined in config.py now
src/arch/mips/process.cc:
adjust process so SMT threads get their own stack space
src/arch/mips/process.hh:
add stack_start static variable
--HG--
extra : convert_revision : 73fdf3da9831d86536651835d209806c7f0d59da
Diffstat (limited to 'src/cpu/exetrace.cc')
0 files changed, 0 insertions, 0 deletions