Merge python and x86 changes with cache branch

--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233

1 files changed, 8 insertions, 46 deletions

diff --git a/src/cpu/func_unit.cc b/src/cpu/func_unit.cc
index c20578a43..d7aeb5b37 100644
--- a/src/cpu/func_unit.cc
+++ b/src/cpu/func_unit.cc
@@ -32,7 +32,8 @@
 
 #include "base/misc.hh"
 #include "cpu/func_unit.hh"
-#include "sim/builder.hh"
+#include "params/OpDesc.hh"
+#include "params/FUDesc.hh"
 
 using namespace std;
 
@@ -116,56 +117,17 @@ FuncUnit::issueLatency(OpClass capability)
 //
 //  The operation-class description object
 //
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
-
-    SimpleEnumParam<OpClass> opClass;
-    Param<unsigned>    opLat;
-    Param<unsigned>    issueLat;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OpDesc)
-
-    INIT_ENUM_PARAM(opClass, "type of operation", opClassStrings),
-    INIT_PARAM(opLat,        "cycles until result is available"),
-    INIT_PARAM(issueLat,     "cycles until another can be issued")
-
-END_INIT_SIM_OBJECT_PARAMS(OpDesc)
-
-
-CREATE_SIM_OBJECT(OpDesc)
+OpDesc *
+OpDescParams::create()
 {
-    return new OpDesc(getInstanceName(), opClass, opLat, issueLat);
+    return new OpDesc(name, opClass, opLat, issueLat);
 }
 
-REGISTER_SIM_OBJECT("OpDesc", OpDesc)
-
-
 //
 //  The FuDesc object
 //
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
-
-    SimObjectVectorParam<OpDesc *> opList;
-    Param<unsigned>                count;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FUDesc)
-
-    INIT_PARAM(opList, "list of operation classes for this FU type"),
-    INIT_PARAM(count,  "number of these FU's available")
-
-END_INIT_SIM_OBJECT_PARAMS(FUDesc)
-
-
-CREATE_SIM_OBJECT(FUDesc)
+FUDesc *
+FUDescParams::create()
 {
-    return new FUDesc(getInstanceName(), opList, count);
+    return new FUDesc(name, opList, count);
 }
-
-REGISTER_SIM_OBJECT("FUDesc", FUDesc)
-