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| author | Dibakar Gope <gope@wisc.edu> | 2015-04-13 17:33:57 -0500 |
|---|---|---|
| committer | Dibakar Gope <gope@wisc.edu> | 2015-04-13 17:33:57 -0500 |
| commit | 34ad1123ee5927e3b1503f07649620a533d3eab9 (patch) | |
| tree | e655941704abbbafad01966bfa188449a336aaef /src/cpu/inorder/InOrderCPU.py | |
| parent | e596e524985cfb1f4d46aceebe69bb7fcd94cf04 (diff) | |
| download | gem5-34ad1123ee5927e3b1503f07649620a533d3eab9.tar.xz | |
cpu: re-organizes the branch predictor structure.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/cpu/inorder/InOrderCPU.py')
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index 920b9cdc1..dddcbbcec 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -29,7 +29,7 @@ from m5.params import * from m5.proxy import * from BaseCPU import BaseCPU -from BranchPredictor import BranchPredictor +from BranchPredictor import * class ThreadModel(Enum): vals = ['Single', 'SMT', 'SwitchOnCacheMiss'] @@ -72,6 +72,6 @@ class InOrderCPU(BaseCPU): div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations") div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations") - branchPred = Param.BranchPredictor(BranchPredictor(numThreads = + branchPred = Param.BranchPredictor(TournamentBP(numThreads = Parent.numThreads), "Branch Predictor") |