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| author | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:25:13 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:25:13 -0500 |
| commit | 0e96798fe0a56936f8590dbd301f2b07a1850e22 (patch) | |
| tree | ffa02a11f4812012b8d3dd4abd6f71d933e19999 /src/cpu/inorder/InOrderCPU.py | |
| parent | 7b3b362ba5d2690324abd58c883fd1d5fe4dc767 (diff) | |
| download | gem5-0e96798fe0a56936f8590dbd301f2b07a1850e22.tar.xz | |
configs/inorder: add options for switch-on-miss to inorder cpu
Diffstat (limited to 'src/cpu/inorder/InOrderCPU.py')
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index a0b0466a7..d6db346d4 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -30,10 +30,15 @@ from m5.params import * from m5.proxy import * from BaseCPU import BaseCPU +class ThreadModel(Enum): + vals = ['Single', 'SMT', 'SwitchOnCacheMiss'] + class InOrderCPU(BaseCPU): type = 'InOrderCPU' activity = Param.Unsigned(0, "Initial count") + threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)") + cachePorts = Param.Unsigned(2, "Cache Ports") stageWidth = Param.Unsigned(1, "Stage width") |