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| author | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:08:18 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:08:18 -0500 |
| commit | 0c6a679359fa84060b5bc745a737073890d2fb90 (patch) | |
| tree | 26590e8ce2b1e63d8f7696b3137cfbbec24158b4 /src/cpu/inorder/InOrderCPU.py | |
| parent | 8ac717ef4c22580516d54046f9c0c1048eb4da62 (diff) | |
| download | gem5-0c6a679359fa84060b5bc745a737073890d2fb90.tar.xz | |
inorder: stage width as a python parameter
allow the user to specify how many instructions a pipeline stage can process
on any given cycle (stageWidth...i.e.bandwidth) by setting the parameter through
the python interface rather than compile the code after changing the *.cc file.
(we always had the parameter there, but still used the static 'ThePipeline::StageWidth'
instead)
-
Since StageWidth is now dynamically defined, change the interstage communication
structure to use a vector and get rid of array and array handling index (toNextStageIndex)
since we can just make calls to the list for the same information
Diffstat (limited to 'src/cpu/inorder/InOrderCPU.py')
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index 8e25891e7..5d24ae4fd 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -40,7 +40,7 @@ class InOrderCPU(BaseCPU): threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)") cachePorts = Param.Unsigned(2, "Cache Ports") - stageWidth = Param.Unsigned(1, "Stage width") + stageWidth = Param.Unsigned(4, "Stage width") fetchMemPort = Param.String("icache_port" , "Name of Memory Port to get instructions from") dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from") |