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| author | Christopher Torng <clt67@cornell.edu> | 2014-03-01 23:35:23 -0600 |
|---|---|---|
| committer | Christopher Torng <clt67@cornell.edu> | 2014-03-01 23:35:23 -0600 |
| commit | 919baa603d0b835c3202f9968a617a31f9116549 (patch) | |
| tree | e5e075957313bbe9a9630b84e64c86545351e264 /src/cpu/inorder/InOrderCPU.py | |
| parent | a533f3f9831081625626f96f9434a00f3079e98e (diff) | |
| download | gem5-919baa603d0b835c3202f9968a617a31f9116549.tar.xz | |
cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPU
A copyRegs() function is added to MIPS utilities
to copy architectural state from the old CPU to
the new CPU during fast-forwarding. This
addition alone enables fast-forwarding for the
o3 cpu model running MIPS.
The patch also adds takeOverFrom() and
drainResume() functions to the InOrderCPU to
enable it to take over from another CPU. This
change enables fast-forwarding for the inorder
cpu model running MIPS, but not for Alpha.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/cpu/inorder/InOrderCPU.py')
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index 4caf254c4..920b9cdc1 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -47,6 +47,10 @@ class InOrderCPU(BaseCPU): def require_caches(cls): return True + @classmethod + def support_take_over(cls): + return True + threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)") cachePorts = Param.Unsigned(2, "Cache Ports") |