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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
| commit | f41df0ee08467711c613faadf9879052ab7196ed (patch) | |
| tree | b5ad5be9cecdec14d6f646e099edf9efcc8b38b0 /src/cpu/inorder/SConscript | |
| parent | 5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1 (diff) | |
| download | gem5-f41df0ee08467711c613faadf9879052ab7196ed.tar.xz | |
inorder-o3: allow both to compile together
allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
Diffstat (limited to 'src/cpu/inorder/SConscript')
| -rw-r--r-- | src/cpu/inorder/SConscript | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript index af237a777..9403aa914 100644 --- a/src/cpu/inorder/SConscript +++ b/src/cpu/inorder/SConscript @@ -35,7 +35,6 @@ if 'InOrderCPU' in env['CPU_MODELS']: SimObject('InOrderTrace.py') TraceFlag('ResReqCount') - TraceFlag('FreeList') TraceFlag('InOrderStage') TraceFlag('InOrderStall') TraceFlag('InOrderCPU') @@ -81,10 +80,6 @@ if 'InOrderCPU' in env['CPU_MODELS']: Source('resources/mult_div_unit.cc') Source('resource_pool.cc') Source('reg_dep_map.cc') - Source('../o3/btb.cc') - Source('../o3/tournament_pred.cc') - Source('../o3/2bit_local_pred.cc') - Source('../o3/ras.cc') Source('thread_context.cc') Source('cpu.cc') |