inorder: stage width as a python parameter

allow the user to specify how many instructions a pipeline stage can process
on any given cycle (stageWidth...i.e.bandwidth) by setting the parameter through
the python interface rather than compile the code after changing the *.cc file.
(we always had the parameter there, but still used the static 'ThePipeline::StageWidth'
instead)
-
Since StageWidth is now dynamically defined, change the interstage communication
structure to use a vector and get rid of array and array handling index (toNextStageIndex)
since we can just make calls to the list for the same information

1 files changed, 5 insertions, 6 deletions

diff --git a/src/cpu/inorder/comm.hh b/src/cpu/inorder/comm.hh
index 386046d1c..ba9322079 100644
--- a/src/cpu/inorder/comm.hh
+++ b/src/cpu/inorder/comm.hh
@@ -44,8 +44,7 @@
 /** Struct that defines the information passed from in between stages */
 /** This information mainly goes forward through the pipeline. */
 struct InterStageStruct {
-    int size;
-    ThePipeline::DynInstPtr insts[ThePipeline::StageWidth];
+    std::vector<ThePipeline::DynInstPtr> insts;
     bool squash;
     bool branchMispredict;
     bool branchTaken;
@@ -55,10 +54,10 @@ struct InterStageStruct {
     bool includeSquashInst;
 
     InterStageStruct()
-        :size(0),  squash(false),
-         branchMispredict(false), branchTaken(false),
-         mispredPC(0), nextPC(0),
-         squashedSeqNum(0), includeSquashInst(false)
+        : squash(false),
+          branchMispredict(false), branchTaken(false),
+          mispredPC(0), nextPC(0),
+          squashedSeqNum(0), includeSquashInst(false)
     { }
 
 };