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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
commit | 25884a87733cd35ef6613aaef9a8a08194267552 (patch) | |
tree | 3eb831102c76206ba5ba4e19b94810be67ce108f /src/cpu/inorder/cpu.cc | |
parent | 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (diff) | |
download | gem5-25884a87733cd35ef6613aaef9a8a08194267552.tar.xz |
Registers: Get rid of the float register width parameter.
Diffstat (limited to 'src/cpu/inorder/cpu.cc')
-rw-r--r-- | src/cpu/inorder/cpu.cc | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 51d62e179..fc8723829 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -890,16 +890,15 @@ InOrderCPU::readIntReg(int reg_idx, ThreadID tid) } FloatReg -InOrderCPU::readFloatReg(int reg_idx, ThreadID tid, int width) +InOrderCPU::readFloatReg(int reg_idx, ThreadID tid) { - - return floatRegFile[tid].readReg(reg_idx, width); + return floatRegFile[tid].readReg(reg_idx); } FloatRegBits -InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid, int width) +InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid) {; - return floatRegFile[tid].readRegBits(reg_idx, width); + return floatRegFile[tid].readRegBits(reg_idx); } void @@ -910,17 +909,16 @@ InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid) void -InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid, int width) +InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid) { - floatRegFile[tid].setReg(reg_idx, val, width); + floatRegFile[tid].setReg(reg_idx, val); } void -InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid, - int width) +InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid) { - floatRegFile[tid].setRegBits(reg_idx, val, width); + floatRegFile[tid].setRegBits(reg_idx, val); } uint64_t |