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authorGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-08 23:02:20 -0700
commit32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (patch)
tree0868fb00a7546d90971bc18acd4f7b0bbce558c0 /src/cpu/inorder/cpu.cc
parent3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (diff)
downloadgem5-32daf6fc3fd34af0023ae74c2a1f8dd597f87242.tar.xz
Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
Diffstat (limited to 'src/cpu/inorder/cpu.cc')
-rw-r--r--src/cpu/inorder/cpu.cc22
1 files changed, 10 insertions, 12 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 3d7d713e8..51d62e179 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -168,7 +168,6 @@ InOrderCPU::InOrderCPU(Params *params)
coreType("default"),
_status(Idle),
tickEvent(this),
- miscRegFile(this),
timeBuffer(2 , 2),
removeInstsThisCycle(false),
activityRec(params->name, NumStages, 10, params->activity),
@@ -267,15 +266,11 @@ InOrderCPU::InOrderCPU(Params *params)
intRegFile[tid].clear();
floatRegFile[tid].clear();
- }
+ isa[tid].clear();
- // Update miscRegFile if necessary
- if (numThreads > 1) {
- miscRegFile.expandForMultithreading(numThreads, numVirtProcs);
+ isa[tid].expandForMultithreading(numThreads, numVirtProcs);
}
- miscRegFile.clear();
-
lastRunningCycle = curTick;
contextSwitch = false;
@@ -461,7 +456,10 @@ InOrderCPU::readFunctional(Addr addr, uint32_t &buffer)
void
InOrderCPU::reset()
{
- miscRegFile.reset(coreType, numThreads, numVirtProcs, dynamic_cast<BaseCPU*>(this));
+ for (int i = 0; i < numThreads; i++) {
+ isa[i].reset(coreType, numThreads,
+ numVirtProcs, dynamic_cast<BaseCPU*>(this));
+ }
}
Port*
@@ -966,25 +964,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
MiscReg
InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
{
- return miscRegFile.readRegNoEffect(misc_reg, tid);
+ return isa[tid].readMiscRegNoEffect(misc_reg);
}
MiscReg
InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
{
- return miscRegFile.readReg(misc_reg, tcBase(tid), tid);
+ return isa[tid].readMiscReg(misc_reg, tcBase(tid));
}
void
InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
{
- miscRegFile.setRegNoEffect(misc_reg, val, tid);
+ isa[tid].setMiscRegNoEffect(misc_reg, val);
}
void
InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
{
- miscRegFile.setReg(misc_reg, val, tcBase(tid), tid);
+ isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
}