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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
commit | a480ba00b96f4c2e872f5a01bfa1782500f1066e (patch) | |
tree | 9d99a96528f37eb601f6e7268c3a359d84f02d57 /src/cpu/inorder/cpu.cc | |
parent | 0cb180ea0dcece9157ad71b4136d557c2dbcf209 (diff) | |
download | gem5-a480ba00b96f4c2e872f5a01bfa1782500f1066e.tar.xz |
Registers: Eliminate the ISA defined integer register file.
Diffstat (limited to 'src/cpu/inorder/cpu.cc')
-rw-r--r-- | src/cpu/inorder/cpu.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 248e78314..36de86986 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -264,7 +264,7 @@ InOrderCPU::InOrderCPU(Params *params) squashSeqNum[tid] = MaxAddr; lastSquashCycle[tid] = 0; - intRegFile[tid].clear(); + memset(intRegs[tid], 0, sizeof(intRegs[tid])); memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid])); isa[tid].clear(); @@ -886,7 +886,7 @@ InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid) uint64_t InOrderCPU::readIntReg(int reg_idx, ThreadID tid) { - return intRegFile[tid].readReg(reg_idx); + return intRegs[tid][reg_idx]; } FloatReg @@ -904,7 +904,7 @@ InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid) void InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid) { - intRegFile[tid].setReg(reg_idx, val); + intRegs[tid][reg_idx] = val; } |