inorder-alpha-port: initial inorder support of ALPHA

Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)

1 files changed, 35 insertions, 2 deletions

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 0b38f39bc..83e94e74d 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -180,15 +180,26 @@ InOrderCPU::InOrderCPU(Params *params)
     // Bind the fetch & data ports from the resource pool.
     fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
     if (fetchPortIdx == 0) {
-        warn("Unable to find port to fetch instructions from.\n");
+        fatal("Unable to find port to fetch instructions from.\n");
     }
 
     dataPortIdx = resPool->getPortIdx(params->dataMemPort);
     if (dataPortIdx == 0) {
-        warn("Unable to find port for data.\n");
+        fatal("Unable to find port for data.\n");
     }
 
 
+    // Hard-Code Bindings to ITB & DTB
+    itbIdx = resPool->getResIdx(name() + "."  + "I-TLB");
+    if (itbIdx == 0) {
+        fatal("Unable to find ITB resource.\n");
+    }
+
+    dtbIdx = resPool->getResIdx(name() + "."  + "D-TLB");
+    if (dtbIdx == 0) {
+        fatal("Unable to find DTB resource.\n");
+    }
+
     for (int i = 0; i < numThreads; ++i) {
         if (i < params->workload.size()) {
             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
@@ -814,6 +825,13 @@ InOrderCPU::removeThread(unsigned tid)
     /** Broadcast to CPU resources*/
 }
 
+PipelineStage*
+InOrderCPU::getPipeStage(int stage_num)
+{
+    return pipelineStage[stage_num];
+}
+
+
 void
 InOrderCPU::activateWhenReady(int tid)
 {
@@ -1245,3 +1263,18 @@ InOrderCPU::write(DynInstPtr inst)
     Resource *mem_res = resPool->getResource(dataPortIdx);
     return mem_res->doDataAccess(inst);
 }
+
+TheISA::ITB*
+InOrderCPU::getITBPtr()
+{
+    TLBUnit *itb_res = dynamic_cast<TLBUnit*>(resPool->getResource(itbIdx));
+    return dynamic_cast<TheISA::ITB*>(itb_res->tlb());
+}
+
+
+TheISA::DTB*
+InOrderCPU::getDTBPtr()
+{
+    TLBUnit *dtb_res = dynamic_cast<TLBUnit*>(resPool->getResource(dtbIdx));
+    return dynamic_cast<TheISA::DTB*>(dtb_res->tlb());
+}