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authorSteve Reinhardt <steve.reinhardt@amd.com>2013-10-15 14:22:43 -0400
committerSteve Reinhardt <steve.reinhardt@amd.com>2013-10-15 14:22:43 -0400
commit06d246ab4ad79c01cb0b1304dbe9415496285b1b (patch)
tree33573a27939a154c6c5cae662592bf37d4c825e1 /src/cpu/inorder/cpu.cc
parent7aa423acad07f05ee547117406a72a5c1b4f6015 (diff)
downloadgem5-06d246ab4ad79c01cb0b1304dbe9415496285b1b.tar.xz
cpu/inorder: merge register class enums
The previous patch introduced a RegClass enum to clean up register classification. The inorder model already had an equivalent enum (RegType) that was used internally. This patch replaces RegType with RegClass to get rid of the now-redundant code.
Diffstat (limited to 'src/cpu/inorder/cpu.cc')
-rw-r--r--src/cpu/inorder/cpu.cc9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 233d532dd..32ca2caaf 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1257,21 +1257,20 @@ InOrderCPU::getPipeStage(int stage_num)
RegIndex
-InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
+InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegClass &reg_type, ThreadID tid)
{
RegIndex rel_idx;
- switch (regIdxToClass(reg_idx, &rel_idx)) {
+ reg_type = regIdxToClass(reg_idx, &rel_idx);
+
+ switch (reg_type) {
case IntRegClass:
- reg_type = IntType;
return isa[tid]->flattenIntIndex(rel_idx);
case FloatRegClass:
- reg_type = FloatType;
return isa[tid]->flattenFloatIndex(rel_idx);
case MiscRegClass:
- reg_type = MiscType;
return rel_idx;
default: