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authorKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:34 -0400
committerKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:34 -0400
commit085f30ff9c81dcb8510185d5493314722d8e378c (patch)
tree8faec2db171b4c6fd36c9aa0d953ee44700c93d6 /src/cpu/inorder/cpu.cc
parent3c417ea23a7b87d3a01a1820c1f00645bb76eeb7 (diff)
downloadgem5-085f30ff9c81dcb8510185d5493314722d8e378c.tar.xz
inorder: scheduling for nonspec insts
make handling of speculative and nonspeculative insts more explicit
Diffstat (limited to 'src/cpu/inorder/cpu.cc')
-rw-r--r--src/cpu/inorder/cpu.cc60
1 files changed, 39 insertions, 21 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index f9f7d6145..bd93d4462 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -425,6 +425,8 @@ InOrderCPU::createBackEndSked(DynInstPtr inst)
}
}
+ //@todo: schedule non-spec insts to operate on this cycle
+ // as long as all previous insts are done
if ( inst->isNonSpeculative() ) {
// skip execution of non speculative insts until later
} else if ( inst->isMemRef() ) {
@@ -437,32 +439,48 @@ InOrderCPU::createBackEndSked(DynInstPtr inst)
X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
}
- if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
- X.needs(MDU, MultDivUnit::EndMultDiv);
- }
-
// MEMORY
- if ( inst->isLoad() ) {
- M.needs(DCache, CacheUnit::InitiateReadData);
- } else if ( inst->isStore() ) {
- if ( inst->numSrcRegs() >= 2 ) {
- M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
+ if (!inst->isNonSpeculative()) {
+ if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
+ M.needs(MDU, MultDivUnit::EndMultDiv);
}
- M.needs(AGEN, AGENUnit::GenerateAddr);
- M.needs(DCache, CacheUnit::InitiateWriteData);
- }
-
- // WRITEBACK
- if ( inst->isLoad() ) {
- W.needs(DCache, CacheUnit::CompleteReadData);
- } else if ( inst->isStore() ) {
- W.needs(DCache, CacheUnit::CompleteWriteData);
+ if ( inst->isLoad() ) {
+ M.needs(DCache, CacheUnit::InitiateReadData);
+ } else if ( inst->isStore() ) {
+ if ( inst->numSrcRegs() >= 2 ) {
+ M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
+ }
+ M.needs(AGEN, AGENUnit::GenerateAddr);
+ M.needs(DCache, CacheUnit::InitiateWriteData);
+ }
}
- if ( inst->isNonSpeculative() ) {
- if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
- W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
+ // WRITEBACK
+ if (!inst->isNonSpeculative()) {
+ if ( inst->isLoad() ) {
+ W.needs(DCache, CacheUnit::CompleteReadData);
+ } else if ( inst->isStore() ) {
+ W.needs(DCache, CacheUnit::CompleteWriteData);
+ }
+ } else {
+ // Finally, Execute Speculative Data
+ if (inst->isMemRef()) {
+ if (inst->isLoad()) {
+ W.needs(AGEN, AGENUnit::GenerateAddr);
+ W.needs(DCache, CacheUnit::InitiateReadData);
+ W.needs(DCache, CacheUnit::CompleteReadData);
+ } else if (inst->isStore()) {
+ if ( inst->numSrcRegs() >= 2 ) {
+ W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
+ }
+ W.needs(AGEN, AGENUnit::GenerateAddr);
+ W.needs(DCache, CacheUnit::InitiateWriteData);
+ W.needs(DCache, CacheUnit::CompleteWriteData);
+ }
+ } else {
+ W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
+ }
}
W.needs(Grad, GraduationUnit::GraduateInst);