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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:15 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:15 -0400 |
| commit | 1c7e988272efead94d2cfbe3fd65ba454d3e1fc1 (patch) | |
| tree | 55affa4470c6cc8cdadc8da953895a0b3a163a24 /src/cpu/inorder/cpu.cc | |
| parent | f41df0ee08467711c613faadf9879052ab7196ed (diff) | |
| download | gem5-1c7e988272efead94d2cfbe3fd65ba454d3e1fc1.tar.xz | |
inorder-mem: skeleton support for prefetch/writehints
Diffstat (limited to 'src/cpu/inorder/cpu.cc')
| -rw-r--r-- | src/cpu/inorder/cpu.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index c5f06c3b2..e17d82041 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -1264,6 +1264,21 @@ InOrderCPU::write(DynInstPtr inst) return mem_res->doDataAccess(inst); } +void +InOrderCPU::prefetch(DynInstPtr inst) +{ + Resource *mem_res = resPool->getResource(dataPortIdx); + return mem_res->prefetch(inst); +} + +void +InOrderCPU::writeHint(DynInstPtr inst) +{ + Resource *mem_res = resPool->getResource(dataPortIdx); + return mem_res->writeHint(inst); +} + + TheISA::TLB* InOrderCPU::getITBPtr() { |