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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
commit | 25884a87733cd35ef6613aaef9a8a08194267552 (patch) | |
tree | 3eb831102c76206ba5ba4e19b94810be67ce108f /src/cpu/inorder/cpu.hh | |
parent | 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (diff) | |
download | gem5-25884a87733cd35ef6613aaef9a8a08194267552.tar.xz |
Registers: Get rid of the float register width parameter.
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
-rw-r--r-- | src/cpu/inorder/cpu.hh | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index bfc5139cf..bda4c41bd 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -404,19 +404,15 @@ class InOrderCPU : public BaseCPU /** Register file accessors */ uint64_t readIntReg(int reg_idx, ThreadID tid); - FloatReg readFloatReg(int reg_idx, ThreadID tid, - int width = TheISA::SingleWidth); + FloatReg readFloatReg(int reg_idx, ThreadID tid); - FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid, - int width = TheISA::SingleWidth); + FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid); void setIntReg(int reg_idx, uint64_t val, ThreadID tid); - void setFloatReg(int reg_idx, FloatReg val, ThreadID tid, - int width = TheISA::SingleWidth); + void setFloatReg(int reg_idx, FloatReg val, ThreadID tid); - void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid, - int width = TheISA::SingleWidth); + void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid); /** Reads a miscellaneous register. */ MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); |