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| author | Gabe Black <gblack@eecs.umich.edu> | 2012-05-26 13:44:46 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-05-26 13:44:46 -0700 |
| commit | 0cba96ba6a5d7a4dab2a63b14149c49dfbfbb3bc (patch) | |
| tree | 1e4e1372b76ed021060d560c2ee1a474f4b22ef0 /src/cpu/inorder/cpu.hh | |
| parent | eae1e97fb002b44a9d8c46df2da1ddc1d0156ce4 (diff) | |
| download | gem5-0cba96ba6a5d7a4dab2a63b14149c49dfbfbb3bc.tar.xz | |
CPU: Merge the predecoder and decoder.
These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.
--HG--
rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 29fe6bc3b..615d0eb90 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -342,7 +342,7 @@ class InOrderCPU : public BaseCPU TheISA::TLB *getITBPtr(); TheISA::TLB *getDTBPtr(); - TheISA::Decoder *getDecoderPtr(); + TheISA::Decoder *getDecoderPtr(unsigned tid); /** Accessor Type for the SkedCache */ typedef uint32_t SkedID; |