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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:35 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:35 -0400 |
| commit | b195da9345c00c2961558f80715660c0c0a629fc (patch) | |
| tree | 0e3c2dee853e7aa46db1a592b62a9d7934c00c69 /src/cpu/inorder/cpu.hh | |
| parent | d5d4e47f76ec254b89c6b884f5fcbf340d4fed49 (diff) | |
| download | gem5-b195da9345c00c2961558f80715660c0c0a629fc.tar.xz | |
inorder: use setupSquash for misspeculation
implement a clean interface to handle branch misprediction and eventually all pipeline
flushing
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index a1fc2de52..aad701ff4 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -581,6 +581,9 @@ class InOrderCPU : public BaseCPU */ ListIt addInst(DynInstPtr inst); + /** Find instruction on instruction list */ + ListIt findInst(InstSeqNum seq_num, ThreadID tid); + /** Function to tell the CPU that an instruction has completed. */ void instDone(DynInstPtr inst, ThreadID tid); |