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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
| commit | 0cb180ea0dcece9157ad71b4136d557c2dbcf209 (patch) | |
| tree | f65b3376cfe8cdad517f6a2a3a8c9e2cf69c987a /src/cpu/inorder/cpu.hh | |
| parent | 25884a87733cd35ef6613aaef9a8a08194267552 (diff) | |
| download | gem5-0cb180ea0dcece9157ad71b4136d557c2dbcf209.tar.xz | |
Registers: Eliminate the ISA defined floating point register file.
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index bda4c41bd..f4cc72e9c 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -259,7 +259,10 @@ class InOrderCPU : public BaseCPU /** The Register File for the CPU */ TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];; - TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];; + union { + FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; + FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; + } floatRegs; /** ISA state */ TheISA::ISA isa[ThePipeline::MaxThreads]; |