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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:15 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:15 -0400 |
| commit | fe4cd9847db2b2d7d566a921670c92fa39d14136 (patch) | |
| tree | a27928cb7e56f26cdd9bb34899d747ff0a91644f /src/cpu/inorder/cpu.hh | |
| parent | 6211fe5d2ee00dae9cd72d9cccdc900241a8f9a2 (diff) | |
| download | gem5-fe4cd9847db2b2d7d566a921670c92fa39d14136.tar.xz | |
inorder-stc: update interface to handle store conditionals
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 9426171c1..e3bfbb7f0 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -495,7 +495,7 @@ class InOrderCPU : public BaseCPU /** Forwards an instruction write. to the appropriate data * resource (indexes into Resource Pool thru "dataPortIdx") */ - Fault write(DynInstPtr inst); + Fault write(DynInstPtr inst, uint64_t *res = NULL); /** Forwards an instruction prefetch to the appropriate data * resource (indexes into Resource Pool thru "dataPortIdx") |