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authorSteve Reinhardt <steve.reinhardt@amd.com>2013-10-15 14:22:43 -0400
committerSteve Reinhardt <steve.reinhardt@amd.com>2013-10-15 14:22:43 -0400
commit06d246ab4ad79c01cb0b1304dbe9415496285b1b (patch)
tree33573a27939a154c6c5cae662592bf37d4c825e1 /src/cpu/inorder/cpu.hh
parent7aa423acad07f05ee547117406a72a5c1b4f6015 (diff)
downloadgem5-06d246ab4ad79c01cb0b1304dbe9415496285b1b.tar.xz
cpu/inorder: merge register class enums
The previous patch introduced a RegClass enum to clean up register classification. The inorder model already had an equivalent enum (RegType) that was used internally. This patch replaces RegType with RegClass to get rid of the now-redundant code.
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
-rw-r--r--src/cpu/inorder/cpu.hh22
1 files changed, 1 insertions, 21 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 6f189f8c9..d5a31cca8 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -334,9 +334,6 @@ class InOrderCPU : public BaseCPU
/** Dependency Tracker for Integer & Floating Point Regs */
RegDepMap archRegDepMap[ThePipeline::MaxThreads];
- /** Register Types Used in Dependency Tracking */
- enum RegType { IntType, FloatType, MiscType, NumRegTypes};
-
/** Global communication structure */
TimeBuffer<TimeStruct> timeBuffer;
@@ -599,24 +596,7 @@ class InOrderCPU : public BaseCPU
void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
- RegType inline getRegType(RegIndex reg_idx)
- {
- switch (regIdxToClass(reg_idx)) {
- case IntRegClass:
- return IntType;
-
- case FloatRegClass:
- return FloatType;
-
- case MiscRegClass:
- return MiscType;
-
- default:
- panic("register %d out of range\n", reg_idx);
- }
- }
-
- RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
+ RegIndex flattenRegIdx(RegIndex reg_idx, RegClass &reg_type, ThreadID tid);
/** Reads a miscellaneous register. */
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);