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author | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:25:13 -0500 |
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committer | Korey Sewell <ksewell@umich.edu> | 2010-01-31 18:25:13 -0500 |
commit | 0e96798fe0a56936f8590dbd301f2b07a1850e22 (patch) | |
tree | ffa02a11f4812012b8d3dd4abd6f71d933e19999 /src/cpu/inorder/cpu.hh | |
parent | 7b3b362ba5d2690324abd58c883fd1d5fe4dc767 (diff) | |
download | gem5-0e96798fe0a56936f8590dbd301f2b07a1850e22.tar.xz |
configs/inorder: add options for switch-on-miss to inorder cpu
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
-rw-r--r-- | src/cpu/inorder/cpu.hh | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 463ca5445..804054f8c 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -100,6 +100,15 @@ class InOrderCPU : public BaseCPU /** Type of core that this is */ std::string coreType; + // Only need for SE MODE + enum ThreadModel { + Single, + SMT, + SwitchOnCacheMiss + }; + + ThreadModel threadModel; + int readCpuId() { return cpu_id; } void setCpuId(int val) { cpu_id = val; } @@ -117,7 +126,6 @@ class InOrderCPU : public BaseCPU /** Overall CPU status. */ Status _status; - private: /** Define TickEvent for the CPU */ class TickEvent : public Event |