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authorKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:33 -0400
committerKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:33 -0400
commit6df63650956387d88f24122c783438553412768f (patch)
tree4aa1a3de620075e5a9994b6d1ae09da08d554ebc /src/cpu/inorder/cpu.hh
parent19e3eb29154ad17664bfe239423f6ba64c77cf05 (diff)
downloadgem5-6df63650956387d88f24122c783438553412768f.tar.xz
inorder: add types for dependency checks
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
-rw-r--r--src/cpu/inorder/cpu.hh5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 42d8da18c..75d4077d7 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -288,6 +288,9 @@ class InOrderCPU : public BaseCPU
/** Dependency Tracker for Integer & Floating Point Regs */
RegDepMap archRegDepMap[ThePipeline::MaxThreads];
+ /** Register Types Used in Dependency Tracking */
+ enum RegType { IntType, FloatType, MiscType, NumRegTypes};
+
/** Global communication structure */
TimeBuffer<TimeStruct> timeBuffer;
@@ -522,7 +525,7 @@ class InOrderCPU : public BaseCPU
void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
- RegIndex flattenRegIdx(RegIndex reg_idx, ThreadID tid);
+ RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
/** Reads a miscellaneous register. */
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);