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author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:36 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:36 -0400 |
commit | 264e8178ff8e97df4fde62359a01898a8af7ae26 (patch) | |
tree | c9d01b656acd914d12974519440a799de11c443d /src/cpu/inorder/cpu.hh | |
parent | f0f33ae2b9be89c062c1df3c61291aa60151713e (diff) | |
download | gem5-264e8178ff8e97df4fde62359a01898a8af7ae26.tar.xz |
imported patch squash_from_next_stage
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
-rw-r--r-- | src/cpu/inorder/cpu.hh | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 051a790db..c8ac33a89 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -547,6 +547,16 @@ class InOrderCPU : public BaseCPU void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid); + RegType inline getRegType(RegIndex reg_idx) + { + if (reg_idx < TheISA::FP_Base_DepTag) + return IntType; + else if (reg_idx < TheISA::Ctrl_Base_DepTag) + return FloatType; + else + return MiscType; + } + RegIndex flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid); /** Reads a miscellaneous register. */ @@ -617,7 +627,7 @@ class InOrderCPU : public BaseCPU void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid); /** Removes the instruction pointed to by the iterator. */ - inline void squashInstIt(const ListIt &instIt, ThreadID tid); + inline void squashInstIt(const ListIt inst_it, ThreadID tid); /** Cleans up all instructions on the instruction remove list. */ void cleanUpRemovedInsts(); |