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author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:42 -0400 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:42 -0400 |
commit | 7aa423acad07f05ee547117406a72a5c1b4f6015 (patch) | |
tree | a4a9f24bb94a743b0316ea2a907d07daddc4ffc3 /src/cpu/inorder/cpu.hh | |
parent | 4f5775df64b1b16ef4a3a02b12e4ac8a6370baed (diff) | |
download | gem5-7aa423acad07f05ee547117406a72a5c1b4f6015.tar.xz |
cpu: clean up architectural register classification
Move from a poorly documented scheme where the mapping
of unified architectural register indices to register
classes is hardcoded all over to one where there's an
enum for the register classes and a function that
encapsulates the mapping.
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
-rw-r--r-- | src/cpu/inorder/cpu.hh | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index e69c9d47b..6f189f8c9 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2012-2013 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * * The license below extends only to copyright in the software and shall @@ -65,6 +66,7 @@ #include "cpu/o3/rename_map.hh" #include "cpu/activity.hh" #include "cpu/base.hh" +#include "cpu/reg_class.hh" #include "cpu/simple_thread.hh" #include "cpu/timebuf.hh" #include "mem/packet.hh" @@ -599,12 +601,19 @@ class InOrderCPU : public BaseCPU RegType inline getRegType(RegIndex reg_idx) { - if (reg_idx < TheISA::FP_Base_DepTag) + switch (regIdxToClass(reg_idx)) { + case IntRegClass: return IntType; - else if (reg_idx < TheISA::Ctrl_Base_DepTag) + + case FloatRegClass: return FloatType; - else + + case MiscRegClass: return MiscType; + + default: + panic("register %d out of range\n", reg_idx); + } } RegIndex flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid); |