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authorKorey Sewell <ksewell@umich.edu>2011-02-04 00:08:18 -0500
committerKorey Sewell <ksewell@umich.edu>2011-02-04 00:08:18 -0500
commit0c6a679359fa84060b5bc745a737073890d2fb90 (patch)
tree26590e8ce2b1e63d8f7696b3137cfbbec24158b4 /src/cpu/inorder/cpu.hh
parent8ac717ef4c22580516d54046f9c0c1048eb4da62 (diff)
downloadgem5-0c6a679359fa84060b5bc745a737073890d2fb90.tar.xz
inorder: stage width as a python parameter
allow the user to specify how many instructions a pipeline stage can process on any given cycle (stageWidth...i.e.bandwidth) by setting the parameter through the python interface rather than compile the code after changing the *.cc file. (we always had the parameter there, but still used the static 'ThePipeline::StageWidth' instead) - Since StageWidth is now dynamically defined, change the interstage communication structure to use a vector and get rid of array and array handling index (toNextStageIndex) since we can just make calls to the list for the same information
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
-rw-r--r--src/cpu/inorder/cpu.hh3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index c3658373a..9ff0f12ce 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -268,6 +268,9 @@ class InOrderCPU : public BaseCPU
/** The Pipeline Stages for the CPU */
PipelineStage *pipelineStage[ThePipeline::NumStages];
+ /** Width (processing bandwidth) of each stage */
+ int stageWidth;
+
/** Program Counters */
TheISA::PCState pc[ThePipeline::MaxThreads];