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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
| commit | 5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1 (patch) | |
| tree | 7ca2a867dd44c4c4b2e4d7de44ff04ec4cfd88c0 /src/cpu/inorder/cpu.hh | |
| parent | 98b1452058ae7e82df7cb7c0373c62a97981a2b9 (diff) | |
| download | gem5-5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1.tar.xz | |
inorder-unified-tlb: use unified TLB instead of old TLB model
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 7c1ad8264..fda2e4366 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -266,8 +266,8 @@ class InOrderCPU : public BaseCPU /** Communication structure that sits in between pipeline stages */ StageQueue *stageQueue[ThePipeline::NumStages-1]; - TheISA::ITB *getITBPtr(); - TheISA::DTB *getDTBPtr(); + TheISA::TLB *getITBPtr(); + TheISA::TLB *getDTBPtr(); public: |