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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
| commit | a480ba00b96f4c2e872f5a01bfa1782500f1066e (patch) | |
| tree | 9d99a96528f37eb601f6e7268c3a359d84f02d57 /src/cpu/inorder/cpu.hh | |
| parent | 0cb180ea0dcece9157ad71b4136d557c2dbcf209 (diff) | |
| download | gem5-a480ba00b96f4c2e872f5a01bfa1782500f1066e.tar.xz | |
Registers: Eliminate the ISA defined integer register file.
Diffstat (limited to 'src/cpu/inorder/cpu.hh')
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index f4cc72e9c..31010a01f 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -258,11 +258,11 @@ class InOrderCPU : public BaseCPU TheISA::IntReg nextNPC[ThePipeline::MaxThreads]; /** The Register File for the CPU */ - TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];; union { FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; } floatRegs; + TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs]; /** ISA state */ TheISA::ISA isa[ThePipeline::MaxThreads]; |